Datasheet
Table Of Contents
- 1 Hardware Description
- 1.1 Hardware Overview
- 1.2 Analog Front End (AFE)
- 1.3 Digital Computation Engine (CE)
- 1.4 80515 MPU Core
- 1.4.1 Memory Organization and Addressing
- 1.4.2 Special Function Registers (SFRs)
- 1.4.3 Generic 80515 Special Function Registers
- 1.4.4 Special Function Registers (SFRs) Specific to the 71M6531D/F and 71M6532D/F
- 1.4.5 Instruction Set
- 1.4.6 UARTs
- 1.4.7 Timers and Counters
- 1.4.8 WD Timer (Software Watchdog Timer)
- 1.4.9 Interrupts
- 1.5 On-Chip Resources
- 1.5.1 Oscillator
- 1.5.2 Internal Clocks
- 1.5.3 Real-Time Clock (RTC)
- 1.5.4 Temperature Sensor
- 1.5.5 Physical Memory
- 1.5.6 Optical Interface
- 1.5.7 Digital I/O – 71M6531D/F
- 1.5.8 Digital I/O – 71M6532D/F
- 1.5.9 Digital IO – Common Characteristics for 71M6531D/F and 71M6532D/F
- 1.5.10 LCD Drivers – 71M6531D/F
- 1.5.11 LCD Drivers – 71M6532D/F
- 1.5.12 LCD Drivers – Common Characteristics for 71M6531D/F and 71M6532D/F
- 1.5.13 Battery Monitor
- 1.5.14 EEPROM Interface
- 1.5.15 SPI Slave Port
- 1.5.16 Hardware Watchdog Timer
- 1.5.17 Test Ports (TMUXOUT pin)
- 2 Functional Description
- 3 Application Information
- 3.1 Connection of Sensors
- 3.2 Connecting 5-V Devices
- 3.3 Temperature Measurement
- 3.4 Temperature Compensation
- 3.5 Connecting LCDs
- 3.6 Connecting I2C EEPROMs
- 3.7 Connecting Three-Wire EEPROMs
- 3.8 UART0 (TX/RX)
- 3.9 Optical Interface (UART1)
- 3.10 Connecting the V1 Pin
- 3.11 Connecting the Reset Pin
- 3.12 Connecting the Emulator Port Pins
- 3.13 Connecting a Battery
- 3.14 Flash Programming
- 3.15 MPU Firmware
- 3.16 Crystal Oscillator
- 3.17 Meter Calibration
- 4 Firmware Interface
- 4.1 I/O RAM and SFR Map – Functional Order
- 4.2 I/O RAM Description – Alphabetical Order
- 4.3 CE Interface Description
- 5 Electrical Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 Recommended External Components
- 5.3 Recommended Operating Conditions
- 5.4 Performance Specifications
- 5.4.1 Input Logic Levels
- 5.4.2 Output Logic Levels
- 5.4.3 Power-Fault Comparator
- 5.4.4 Battery Monitor
- 5.4.5 Supply Current
- 5.4.6 V3P3D Switch
- 5.4.7 2.5 V Voltage Regulator
- 5.4.8 Low-Power Voltage Regulator
- 5.4.9 Crystal Oscillator
- 5.4.10 LCD DAC
- 5.4.11 LCD Drivers
- 5.4.12 Optical Interface
- 5.4.13 Temperature Sensor
- 5.4.14 VREF
- 5.4.15 ADC Converter, V3P3A Referenced
- 5.5 Timing Specifications
- 5.6 Typical Performance Data
- 5.7 71M6531D/F Package
- 5.8 71M6532D/F Package
- 5.9 Pin Descriptions
- 6 Ordering Information
- 7 Related Information
- 8 Contact Information
- Appendix A: Acronyms
- Appendix B: Revision History
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
Rev 2 45
Additionally, if DIO6 and DIO7 are configured as DIO and defined as outputs, they can be used as
dedicated pulse outputs (WPULSE = DIO6, VARPULSE = DIO7) using the DIO_PW and DIO_PV bits. In
this case, DIO6 and DIO7 are under CE control. DIO4 and DIO5 can be configured to implement the
EEPROM Interface.
The PB pin is a dedicated digital input. In addition, if the optical UART is not used, OPT_TX and OPT_RX
can be configured as dedicated DIO pins, DIO1 and DIO2, respectively (see Section 1.5.6 Optical Interface).
The internal control resources selectable for the DIO pins are listed in Table 46. If more than one input is
connected to the same resource, the resources are combined using a logical OR.
Tracking DIO pins configured as outputs is useful for pulse counting without external hardware.
Either the interrupts or the counter/timer clocks can be used to count pulses on the pulse outputs
or interrupts on the CE’s power failure output.
When driving LEDs, relay coils etc., the DIO pins should sink the current into GNDD (as shown in
Figure 10, right), not source it from V3P3D (as shown in Figure 10, left). This is due to the resis-
tance of the internal switch that connects V3P3D to either V3P3SYS or VBAT.
Sourcing current into or out of DIO pins other than the PB pin, for example with pull-up or pull-
down resistors, should be avoided. Violating this rule will lead to increased quiescent current in
SLEEP and LCD modes.
Figure 10: Connecting an External Load to DIO Pins
1.5.10 LCD Drivers – 71M6531D/F
The 71M6531 contains a total of 39 dedicated and multiplexed LCD drivers which are grouped as follows:
• 11 dedicated LCD segment drivers – always available
• 3 drivers multiplexed with the ICE interface (E_TCLK, E_RST, E_RXTX) – available in normal operation
mode (when not emulating)
• 2 driver multiplexed with auxiliary signals MUX_SYNC and CKTEST (SEG7, SEG19) – available
when not used for test
• 4 drivers multiplexed with the SPI port (PCLK, PSDO, PCSZ, PSDI)
• 19 multi-use pins described in Section 1.5.7 Digital I/O – 71M6531D/F.
• 4 common drivers for multiplexing (25%, 33%, 50%, or 100% duty cycle) – always available
With a minimum of 16 driver pins always available and a total of 39 driver pins in the maximum configuration,
the device is capable of driving between 64 to 156 pixels of LCD display with 25% duty cycle. At eight pixels
per digit, this corresponds to 8 to 19 digits. At 33% duty cycle, 48 to 117 pixels can be driven.
For each multi-use pin, the corresponding LCD_BITMAP[] bit (see Section 1.5.7 Digital I/O – 71M6531D/F),
is used to select the pin for DIO or LCD operation. The mapping of the LCD_BITMAP[] bits is specified in
V3P3SYS
VBAT
V3P3D
DIO
GNDD
MISSION
BROWNOUT
LCD/SLEEP
LOW
HIGH
HIGH-Z
V3P3SYS
VBAT
V3P3D
DIO
GNDD
MISSION
BROWNOUT
LCD/SLEEP
LOW
HIGH
HIGH-Z