Datasheet
Table Of Contents
- 1 Hardware Description
- 1.1 Hardware Overview
- 1.2 Analog Front End (AFE)
- 1.3 Digital Computation Engine (CE)
- 1.4 80515 MPU Core
- 1.4.1 Memory Organization and Addressing
- 1.4.2 Special Function Registers (SFRs)
- 1.4.3 Generic 80515 Special Function Registers
- 1.4.4 Special Function Registers (SFRs) Specific to the 71M6531D/F and 71M6532D/F
- 1.4.5 Instruction Set
- 1.4.6 UARTs
- 1.4.7 Timers and Counters
- 1.4.8 WD Timer (Software Watchdog Timer)
- 1.4.9 Interrupts
- 1.5 On-Chip Resources
- 1.5.1 Oscillator
- 1.5.2 Internal Clocks
- 1.5.3 Real-Time Clock (RTC)
- 1.5.4 Temperature Sensor
- 1.5.5 Physical Memory
- 1.5.6 Optical Interface
- 1.5.7 Digital I/O – 71M6531D/F
- 1.5.8 Digital I/O – 71M6532D/F
- 1.5.9 Digital IO – Common Characteristics for 71M6531D/F and 71M6532D/F
- 1.5.10 LCD Drivers – 71M6531D/F
- 1.5.11 LCD Drivers – 71M6532D/F
- 1.5.12 LCD Drivers – Common Characteristics for 71M6531D/F and 71M6532D/F
- 1.5.13 Battery Monitor
- 1.5.14 EEPROM Interface
- 1.5.15 SPI Slave Port
- 1.5.16 Hardware Watchdog Timer
- 1.5.17 Test Ports (TMUXOUT pin)
- 2 Functional Description
- 3 Application Information
- 3.1 Connection of Sensors
- 3.2 Connecting 5-V Devices
- 3.3 Temperature Measurement
- 3.4 Temperature Compensation
- 3.5 Connecting LCDs
- 3.6 Connecting I2C EEPROMs
- 3.7 Connecting Three-Wire EEPROMs
- 3.8 UART0 (TX/RX)
- 3.9 Optical Interface (UART1)
- 3.10 Connecting the V1 Pin
- 3.11 Connecting the Reset Pin
- 3.12 Connecting the Emulator Port Pins
- 3.13 Connecting a Battery
- 3.14 Flash Programming
- 3.15 MPU Firmware
- 3.16 Crystal Oscillator
- 3.17 Meter Calibration
- 4 Firmware Interface
- 4.1 I/O RAM and SFR Map – Functional Order
- 4.2 I/O RAM Description – Alphabetical Order
- 4.3 CE Interface Description
- 5 Electrical Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 Recommended External Components
- 5.3 Recommended Operating Conditions
- 5.4 Performance Specifications
- 5.4.1 Input Logic Levels
- 5.4.2 Output Logic Levels
- 5.4.3 Power-Fault Comparator
- 5.4.4 Battery Monitor
- 5.4.5 Supply Current
- 5.4.6 V3P3D Switch
- 5.4.7 2.5 V Voltage Regulator
- 5.4.8 Low-Power Voltage Regulator
- 5.4.9 Crystal Oscillator
- 5.4.10 LCD DAC
- 5.4.11 LCD Drivers
- 5.4.12 Optical Interface
- 5.4.13 Temperature Sensor
- 5.4.14 VREF
- 5.4.15 ADC Converter, V3P3A Referenced
- 5.5 Timing Specifications
- 5.6 Typical Performance Data
- 5.7 71M6531D/F Package
- 5.8 71M6532D/F Package
- 5.9 Pin Descriptions
- 6 Ordering Information
- 7 Related Information
- 8 Contact Information
- Appendix A: Acronyms
- Appendix B: Revision History
Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005
50 Rev 2
Table 49: SPI Command Description
Command
Description
11xx xxxx ADDR Byte0 ... ByteN
Read data starting at ADDR. The ADDR will auto-increment until PCSZ
is raised. Upon completion:
SP__CMD=11xx xxxx, SP_ADDR=ADDR+N+1.
No MPU interrupt is generated if the command is 1100 0000. Otherwise,
an SPI interrupt is generated.
10xx xxxx ADDR Byte0 ... ByteN
Write data starting at ADDR. The ADDR will auto-increment until PCSZ
is raised. Upon completion:
SP_CMD=10xx xxxx, SP_ADDR=ADDR+N+1.
No MPU interrupt is generated if the command is 1000 0000. Otherwise,
an SPI interrupt is generated.
Certain I/O RAM registers can be written and read using the SPI port (see Table 50). However, the MPU
takes priority over the I/O RAM bus, and SPI operation may fail without notice. To avoid this situation, the
SPI host should send a command other than 11xxxxxx or 10xxxxxx (read or write) before the actual read
or write command. The SPI slave interface will load the command register and generate an INT2 inter-
rupt upon receiving the command. The MPU should service the interrupt and halt any external data memory
operations to effectively grant the bus to the SPI. When the SPI host finishes, it should send another
command so the MPU can release the bus. There are no issues with Data RAM access; SPI and the
MPU will share the bus with no conflicts for Data RAM access.
Table 50: I/O RAM Registers Accessible via SPI
Name Address (hex) Bit Range Read/Write
CE0
2000
7:3
RW
CE1
2001
7:0
RW
CE2
2002
5:3, 1:0
RW
CONFIG0
2004
7:6, 3:0
RW
CONFIG1
2005
5:2, 0
RW
VERSION
2006
7:0
R
CONFIG2
2007
7:0
RW
DIO0
2008
7:6, 4:0
RW
DIO1 to DIO6
2009 to 200E
6:4, 2:0
RW
−
200F
7:6, 3:2
RW
RTM0H
2060
1:0
RW
RTM0L
2061
7:0
RW
RTM1H
2062
1:0
RW
RTM1L
2063
7:0
RW
RTM2H
2064
1:0
RW
RTM2L
2065
7:0
RW
RTM3H
2066
1:0
RW
RTM3L
2067
7:0
RW
PLS_W
2080
7:0
RW
PLS_I
2081
7:0
RW
SLOT0 to SLOT9
2090 to 209A
7:0
RW
CE3
209D
3:0
RW
CE4
20A7
7:0
RW
CE5
20A8
7:0
RW
WAKE
20A9
7:5, 3:0
R
CONFIG3
20AC
5:4, 1:0
RW
CONFIG4
20AD
5:4, 1:0
RW
−
20AF
2:0
RW