Datasheet

FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
Rev 2 55
2.2 System Timing Summary
Figure 19 summarizes the timing relationships between the input MUX states, the CE_BUSY signal and
the two serial output streams. In this example, MUX_DIV[3:0] = 4 and FIR_LEN[1:0] = 2 (384 CE cycles,
3 CK32 cycles per conversion), resulting in 13 CK32 cycles per multiplexer frame. Generally, the duration
of each MUX frame is:
• 1 + MUX_DIV * 1, if FIR_LEN[1:0] = 0 (138 CE cycles)
• 1 + MUX_DIV * 2, if FIR_LEN[1:0] = 1 (288 CE cycles)
• 1 + MUX_DIV * 3, if FIR_LEN[1:0] = 2 (384 CE cycles).
An ADC conversion will always consume an integer number of CK32 clocks. Following this is a single
CK32 cycle where the bandgap voltage is allowed to recover from the change in CROSS.
Figure 19: Timing Relationship between ADC MUX, Compute Engine
Each CE program pass begins when the ADC0 conversion (for IA) begins. Depending on the length of
the CE program, it may continue running until the end of the last conversion (ADC3). CE opcodes are
constructed to ensure that all CE code passes consume exactly the same number of cycles. The result of
each ADC conversion is inserted into the RAM when the conversion is complete. The CE code is written
to tolerate sudden changes in ADC data. The exact clock count when each ADC value is loaded into
RAM is shown in Figure 19.
Figure 20 shows that the serial data stream, RTM, begins transmitting at the beginning of state S. RTM,
consisting of 140 CK cycles, will always finish before the next code pass starts.
FLAG
RTM DATA 0 (32 bits)
0 1
0 1
0 1
0 1
FLAG
FLAG
FLAG
CK32
MUX_SYNC
CKTEST
TMUXOUT/RTM
LSB
LSB
SIGN
SIGN
LSB
SIGN
30 31 30 31
30
31
30 31
LSB
SIGN
RTM DATA 1 (32 bits)
RTM DATA 2 (32 bits)
RTM DATA 3 (32 bits)
Figure 20: RTM Output Format
CK32
MUX STATE
0
MUX_DIV=4 (4 conversions) is shown
Settle
ADC MUX Frame
ADC EXECUTION
S
MUX_SYNC
S
CE_EXECUTION
MAX CK COUNT
0 450
150
900 1350 1800
ADC0 ADC1 ADC2 ADC3
CK COUNT = CE_CYCLES + floor((CE_CYCLES + 2) / 5)
NOTES:
1. ALL DIMENSIONS ARE 5MHZ CK COUNTS.
2. THE PRECISE FREQUENCY OF CK IS 150*CRYSTAL FREQUENCY = 4.9152MHz.
3. XFER_BUSY OCCURS ONCE EVERY (PRE_SAMPS * SUM_CYCLES) CODE PASSES.
CE_BUSY
XFER_BUSY
INITIATED BY A CE OPCODE AT END OF SUMMATION INTERVAL
ADC TIMING
CE TIMING
1 2 3