Datasheet
Table Of Contents
- 1 Hardware Description
- 1.1 Hardware Overview
- 1.2 Analog Front End (AFE)
- 1.3 Digital Computation Engine (CE)
- 1.4 80515 MPU Core
- 1.4.1 Memory Organization and Addressing
- 1.4.2 Special Function Registers (SFRs)
- 1.4.3 Generic 80515 Special Function Registers
- 1.4.4 Special Function Registers (SFRs) Specific to the 71M6531D/F and 71M6532D/F
- 1.4.5 Instruction Set
- 1.4.6 UARTs
- 1.4.7 Timers and Counters
- 1.4.8 WD Timer (Software Watchdog Timer)
- 1.4.9 Interrupts
- 1.5 On-Chip Resources
- 1.5.1 Oscillator
- 1.5.2 Internal Clocks
- 1.5.3 Real-Time Clock (RTC)
- 1.5.4 Temperature Sensor
- 1.5.5 Physical Memory
- 1.5.6 Optical Interface
- 1.5.7 Digital I/O – 71M6531D/F
- 1.5.8 Digital I/O – 71M6532D/F
- 1.5.9 Digital IO – Common Characteristics for 71M6531D/F and 71M6532D/F
- 1.5.10 LCD Drivers – 71M6531D/F
- 1.5.11 LCD Drivers – 71M6532D/F
- 1.5.12 LCD Drivers – Common Characteristics for 71M6531D/F and 71M6532D/F
- 1.5.13 Battery Monitor
- 1.5.14 EEPROM Interface
- 1.5.15 SPI Slave Port
- 1.5.16 Hardware Watchdog Timer
- 1.5.17 Test Ports (TMUXOUT pin)
- 2 Functional Description
- 3 Application Information
- 3.1 Connection of Sensors
- 3.2 Connecting 5-V Devices
- 3.3 Temperature Measurement
- 3.4 Temperature Compensation
- 3.5 Connecting LCDs
- 3.6 Connecting I2C EEPROMs
- 3.7 Connecting Three-Wire EEPROMs
- 3.8 UART0 (TX/RX)
- 3.9 Optical Interface (UART1)
- 3.10 Connecting the V1 Pin
- 3.11 Connecting the Reset Pin
- 3.12 Connecting the Emulator Port Pins
- 3.13 Connecting a Battery
- 3.14 Flash Programming
- 3.15 MPU Firmware
- 3.16 Crystal Oscillator
- 3.17 Meter Calibration
- 4 Firmware Interface
- 4.1 I/O RAM and SFR Map – Functional Order
- 4.2 I/O RAM Description – Alphabetical Order
- 4.3 CE Interface Description
- 5 Electrical Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 Recommended External Components
- 5.3 Recommended Operating Conditions
- 5.4 Performance Specifications
- 5.4.1 Input Logic Levels
- 5.4.2 Output Logic Levels
- 5.4.3 Power-Fault Comparator
- 5.4.4 Battery Monitor
- 5.4.5 Supply Current
- 5.4.6 V3P3D Switch
- 5.4.7 2.5 V Voltage Regulator
- 5.4.8 Low-Power Voltage Regulator
- 5.4.9 Crystal Oscillator
- 5.4.10 LCD DAC
- 5.4.11 LCD Drivers
- 5.4.12 Optical Interface
- 5.4.13 Temperature Sensor
- 5.4.14 VREF
- 5.4.15 ADC Converter, V3P3A Referenced
- 5.5 Timing Specifications
- 5.6 Typical Performance Data
- 5.7 71M6531D/F Package
- 5.8 71M6532D/F Package
- 5.9 Pin Descriptions
- 6 Ordering Information
- 7 Related Information
- 8 Contact Information
- Appendix A: Acronyms
- Appendix B: Revision History
![](/manual/maxim-integrated/71m6531f-im-f/datasheet-english/images/img-57.png)
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
Rev 2 57
To facilitate transition to SLEEP mode, which is useful when an unprogrammed IC is mounted on a PCB
with a battery installed, the production test programs the following six-byte sequence into the flash loca-
tion starting at address 0x00000: 0x74 - 0x40 - 0x90 - 0x20 - 0xA9 - 0xF0. This sequence decodes to the
following assembler code:
0000: 7440 MOV A,#40 ; set bit 6 in accumulator
0002: 9020A9 MOV DPTR,#20A9 ; point to I/O RAM address 0x20A9
0005: F0 MOVX @DPTR,A ; set bit 6 (sleep) in 0x20A9
Transitions from both LCD and SLEEP mode are initiated by the wake-up timer timeout conditions or
pushbutton events. When the PB pin is pulled high (pushbutton is pressed), the IE_PB interrupt flag (SFR
0xE8[4]) is set, and when the wake-up timer times out, the IE_WAKE interrupt flag (SFR 0xE8[5]) is set.
In the absence of system power, if the voltage margin for the LDO regulator providing 2.5 V to the internal
circuitry becomes too low to be safe, the part automatically enters SLEEP mode (BAT_OK false). The bat-
tery voltage must stay above 3 V to ensure that BAT_OK remains true. Under this condition, the
71M6531 stays in SLEEP mode, even if the voltage margin for the LDO improves (BAT_OK true). Table
52 shows the circuit functions available in each operating mode.
Table 52: Available Circuit Functions
Circuit Function
System Power
Battery Power (Nonvolatile Supply)
MISSION BROWNOUT LCD SLEEP
CE
Yes
–
–
–
CE Data RAM
Yes
Yes
–
–
FIR
Yes
–
–
–
Analog circuits
Yes
–
–
–
MPU clock rate
From PLL, as
defined by
MPU_DIV[2:0]
28.672 kHz
(7/8 of 32768 Hz)
– –
MPU_DIV[2:0]
Yes
–
–
–
ICE
Yes
Yes
–
–
DIO Pins
Yes
Yes
–
–
Watchdog Timer
Yes
Yes
–
–
LCD
Yes
Yes
Yes
–
EEPROM Interface (2-wire)
Yes
Yes (8 kb/s)
–
–
EEPROM Interface (3-wire)
Yes
Yes (16 kb/s)
–
–
UART
Yes
300 bd
–
–
Optical TX modulation
Yes
–
–
–
Flash Read
Yes
Yes
–
–
Flash Page Erase
Yes
Yes
–
–
Flash Write
Yes
–
–
–
RAM Read and Write
Yes
Yes
–
–
Wakeup Timer
Yes
Yes
Yes
Yes
OSC and RTC
Yes
Yes
Yes
Yes
XRAM data preservation
Yes
Yes
–
–
V3P3D voltage output pin
Yes
Yes
–
–
GPO – GP7 registers
Yes
Yes
Yes
Yes
– indicates not active
2.3.1 BROWNOUT Mode
In BROWNOUT mode, most non-metering digital functions are active (as shown in Table 52), including
ICE, UART, EEPROM, LCD and RTC. In BROWNOUT mode, a low bias current regulator will provide
2.5 Volts to V2P5 and V2P5NV. The regulator has an output called BAT_OK to indicate that it has sufficient
overhead. When BAT_OK = 0, the part will enter SLEEP mode. From BROWNOUT mode, the processor