Datasheet
Table Of Contents
- 1 Hardware Description
- 1.1 Hardware Overview
- 1.2 Analog Front End (AFE)
- 1.3 Digital Computation Engine (CE)
- 1.4 80515 MPU Core
- 1.4.1 Memory Organization and Addressing
- 1.4.2 Special Function Registers (SFRs)
- 1.4.3 Generic 80515 Special Function Registers
- 1.4.4 Special Function Registers (SFRs) Specific to the 71M6531D/F and 71M6532D/F
- 1.4.5 Instruction Set
- 1.4.6 UARTs
- 1.4.7 Timers and Counters
- 1.4.8 WD Timer (Software Watchdog Timer)
- 1.4.9 Interrupts
- 1.5 On-Chip Resources
- 1.5.1 Oscillator
- 1.5.2 Internal Clocks
- 1.5.3 Real-Time Clock (RTC)
- 1.5.4 Temperature Sensor
- 1.5.5 Physical Memory
- 1.5.6 Optical Interface
- 1.5.7 Digital I/O – 71M6531D/F
- 1.5.8 Digital I/O – 71M6532D/F
- 1.5.9 Digital IO – Common Characteristics for 71M6531D/F and 71M6532D/F
- 1.5.10 LCD Drivers – 71M6531D/F
- 1.5.11 LCD Drivers – 71M6532D/F
- 1.5.12 LCD Drivers – Common Characteristics for 71M6531D/F and 71M6532D/F
- 1.5.13 Battery Monitor
- 1.5.14 EEPROM Interface
- 1.5.15 SPI Slave Port
- 1.5.16 Hardware Watchdog Timer
- 1.5.17 Test Ports (TMUXOUT pin)
- 2 Functional Description
- 3 Application Information
- 3.1 Connection of Sensors
- 3.2 Connecting 5-V Devices
- 3.3 Temperature Measurement
- 3.4 Temperature Compensation
- 3.5 Connecting LCDs
- 3.6 Connecting I2C EEPROMs
- 3.7 Connecting Three-Wire EEPROMs
- 3.8 UART0 (TX/RX)
- 3.9 Optical Interface (UART1)
- 3.10 Connecting the V1 Pin
- 3.11 Connecting the Reset Pin
- 3.12 Connecting the Emulator Port Pins
- 3.13 Connecting a Battery
- 3.14 Flash Programming
- 3.15 MPU Firmware
- 3.16 Crystal Oscillator
- 3.17 Meter Calibration
- 4 Firmware Interface
- 4.1 I/O RAM and SFR Map – Functional Order
- 4.2 I/O RAM Description – Alphabetical Order
- 4.3 CE Interface Description
- 5 Electrical Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 Recommended External Components
- 5.3 Recommended Operating Conditions
- 5.4 Performance Specifications
- 5.4.1 Input Logic Levels
- 5.4.2 Output Logic Levels
- 5.4.3 Power-Fault Comparator
- 5.4.4 Battery Monitor
- 5.4.5 Supply Current
- 5.4.6 V3P3D Switch
- 5.4.7 2.5 V Voltage Regulator
- 5.4.8 Low-Power Voltage Regulator
- 5.4.9 Crystal Oscillator
- 5.4.10 LCD DAC
- 5.4.11 LCD Drivers
- 5.4.12 Optical Interface
- 5.4.13 Temperature Sensor
- 5.4.14 VREF
- 5.4.15 ADC Converter, V3P3A Referenced
- 5.5 Timing Specifications
- 5.6 Typical Performance Data
- 5.7 71M6531D/F Package
- 5.8 71M6532D/F Package
- 5.9 Pin Descriptions
- 6 Ordering Information
- 7 Related Information
- 8 Contact Information
- Appendix A: Acronyms
- Appendix B: Revision History
Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005
6 Rev 2
Tables
Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles ....................................................... 11
Table 2: ADC Resolution ............................................................................................................................. 12
Table 3: ADC RAM Locations ..................................................................................................................... 12
Table 4: XRAM Locations for ADC Results ................................................................................................ 15
Table 5: Meter Equations ............................................................................................................................ 16
Table 6: CKMPU Clock Frequencies .......................................................................................................... 19
Table 7: Memory Map ................................................................................................................................. 20
Table 8: Internal Data Memory Map ........................................................................................................... 21
Table 9: Special Function Register Map ..................................................................................................... 21
Table 10: Generic 80515 SFRs - Location and Reset Values .................................................................... 22
Table 11: PSW Bit Functions (SFR 0xD0) ..................................................................................................... 23
Table 12: Port Registers ............................................................................................................................. 24
Table 13: Stretch Memory Cycle Width ...................................................................................................... 24
Table 14: 71M6531D/F and 71M6532D/F Specific SFRs ........................................................................... 24
Table 15: Baud Rate Generation ................................................................................................................ 26
Table 16: UART Modes ............................................................................................................................... 26
Table 17: The S0CON (UART0) Register (SFR 0x98) ................................................................................. 27
Table 18: The S1CON (UART1) register (SFR 0x9B) .................................................................................. 27
Table 19: PCON Register Bit Description (SFR 0x87) ................................................................................ 28
Table 20: Timers/Counters Mode Description ............................................................................................ 28
Table 21: Allowed Timer/Counter Mode Combinations .............................................................................. 29
Table 22: TMOD Register Bit Description (SFR 0x89) ................................................................................ 29
Table 23: The TCON Register Bit Functions (SFR 0x88) ............................................................................ 29
Table 24: The IEN0 Bit Functions (SFR 0xA8) ............................................................................................ 30
Table 25: The IEN1 Bit Functions (SFR 0xB8) ............................................................................................ 31
Table 26: The IEN2 Bit Functions (SFR 0x9A) ............................................................................................ 31
Table 27: TCON Bit Functions (SFR 0x88) ................................................................................................. 31
Table 28: The T2CON Bit Functions (SFR 0xC8) ........................................................................................ 31
Table 29: The IRCON Bit Functions (SFR 0xC0) ........................................................................................ 31
Table 30: External MPU Interrupts .............................................................................................................. 32
Table 31: Interrupt Enable and Flag Bits .................................................................................................... 32
Table 32: Interrupt Priority Level Groups .................................................................................................... 33
Table 33: Interrupt Priority Levels ............................................................................................................... 33
Table 34: Interrupt Priority Registers (IP0 and IP1) .................................................................................... 34
Table 35: Interrupt Polling Sequence .......................................................................................................... 34
Table 36: Interrupt Vectors.......................................................................................................................... 34
Table 37: Clock System Summary .............................................................................................................. 36
Table 38: Bank Switching with FL_BANK[2:0] ............................................................................................ 40
Table 39: Data/Direction Registers and Internal Resources for DIO 1-15 (71M6531D/F) ......................... 42
Table 40: Data/Direction Registers and Internal Resources for DIO 17-29 (71M6531D/F) ....................... 42
Table 41: Data/Direction Registers and Internal Resources for DIO 43-46 (71M6531D/F) ....................... 42
Table 42: Data/Direction Registers and Internal Resources for DIO 1-15 (71M6532D/F) ......................... 43
Table 43: Data/Direction Registers and Internal Resources for DIO 16-30 (71M6532D/F) ....................... 43
Table 44: Data/Direction Registers and Internal Resources for DIO 40-51 (71M6532D/F) ....................... 44
Table 45: DIO_DIR Control Bit .................................................................................................................... 44
Table 46: Selectable Control using DIO_DIR Bits ......................................................................................... 44
Table 47: EECTRL Bits for 2-pin Interface ................................................................................................... 47
Table 48: EECTRL Bits for the 3-Wire Interface .......................................................................................... 48
Table 49: SPI Command Description .......................................................................................................... 50
Table 50: I/O RAM Registers Accessible via SPI ....................................................................................... 50
Table 51: TMUX[4:0] Selections ................................................................................................................. 53
Table 52: Available Circuit Functions .......................................................................................................... 57