Datasheet

Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005
60 Rev 2
Figure 24: Power-Up Timing with VBAT only
2.4 Fault and Reset Behavior
2.4.1 Reset Mode
When the RESET pin is pulled high, all digital activity stops. The oscillator and RTC module continue to
run. Additionally, all I/O RAM bits are set to their default states. As long as V1, the input voltage at the
power fault block, is greater than VBIAS, the internal 2.5 V regulator will continue to provide power to the
digital section.
Once initiated, the reset mode will persist until the reset timer times out, signified by WAKE rising. This
will occur in 4100 cycles of the real time clock after RESET goes low, at which time the MPU will begin
executing it’s pre-boot and boot sequences from address 00. See the Program Security description in the
Flash Memory section for additional descriptions of pre-boot and boot.
If system power is not present, the reset timer duration will be 2 cycles of the crystal clock at which time
the MPU will begin executing in BROWNOUT mode, starting at address 00.
2.4.2 Power Fault Circuit
The 71M6531D/F and 71M6532D/F include a comparator to monitor system power fault conditions.
When the output of the comparator falls (V1<VBIAS), the I/O RAM bits PLL_OK bit is zeroed and the part
switches to BROWNOUT mode if a battery is present (and the MPU keeps executing code). If a battery is
not present, as indicated by BAT_OK=0, WAKE will fall and the part will enter SLEEP mode. Once sys-
tem power returns, the MPU remains in reset and does not transition to MISSION mode until 2048 to 4096
CK32 clock cycles later, when PLL_OK rises. There are several conditions the device could be in as sys-
tem power returns. If the part is in BROWNOUT mode, it will automatically switch to MISSION mode when
PLL_OK rises. It will receive an interrupt indicating this. No configuration bits will be reset or reconfigured
during this transition.
If the part is in LCD or SLEEP mode when system power returns, it will also switch to MISSION mode
when PLL_OK rises. In this case, all configuration bits will be in the reset state due to WAKE having
been zero. The RTC clock will not be disturbed, but the MPU RAM must be re-initialized. The hardware
watchdog timer will become active when the part enters MISSION mode.
If there is no battery when system power returns, the part will switch to MISSION mode when PLL_OK
rises. All configuration bits will be in reset state and RTC and MPU RAM data will be unknown and must
be initialized by the MPU.