Datasheet

FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
Rev 2 79
Name
Location
Reset
Wake
Dir
Description
DIO_EEX[1:0]
2008[7:6] 0 0 R/W
When set, converts DIO4 and DIO5 to interface with external EEPROM. DIO4 becomes
SDCK and DIO5 becomes bi-directional SDATA.
DIO_EEX[1:0]
Function
00
Disable EEPROM interface
01
2-Wire EEPROM interface
10
3-Wire EEPROM interface
11
not used
DIO_PV
2008[2]
0
0
R/W
Causes VARPULSE to be output on DIO7.
DIO_PW
2008[3]
0
0
R/W
Causes WPULSE to be output on DIO6.
DIO_PX
200F[3]
0
0
R/W
Causes XPULSE to be output on DIO8.
DIO_PY
200F[2]
0
0
R/W
Causes YPULSE to be output on DIO9.
EEDATA[7:0]
SFR 9E
0
0
R/W
Serial EEPROM interface data.
EECTRL[7:0]
SFR 9F
0
0
R/W
Serial EEPROM interface control.
ECK_DIS
2005[5] 0 0 R/W
Emulator clock disable. When ECK_DIS = 1, the emulator clock is disabled.
If ECK_DIS is set, the emulator and programming devices will be unable to
erase or program the device.
EQU[2:0]
2000[7:5]
0
0
R/W
Specifies the power equation to be used by the CE.
EX_XFR
EX_RTC
EX_FWCOL
EX_PLL
2002[0]
2002[1]
2007[4]
2007[5]
0
0
0
0
0
0
0
0
R/W
Interrupt enable bits. These bits enable the XFER_BUSY, the RTC_1SEC, the Firm-
WareCollision (FWCOL) and PLL interrupts. Note that if one of these interrupts is to
be enabled, its corresponding MPU EX enable must also be set. See Section
1.4.9
Interrupts for details.
FIR_LEN[1:0]
2007[3:2] 1 1 R/W
FIR_LEN[1:0] controls the length of the ADC decimation FIR filter and therefore controls
the time taken for each conversion.
[M40MHZ, M26MHZ] FIR_LEN[1:0]
Resulting FIR
Filter Cycles
Resulting
CK32 Cycles
Resulting
DC Gain
[00], [10], or [11]
00
138
1
0.110017
01
288
2
1.000
10
384
3
2.37037
[01]
00
186
1
0.113644
01
384
2
1.000
10
588
3
3.590363
FL_BANK[2:0]
SFR B6[2:0] 1 1 R/W
Flash bank. Memory above 32 KB is mapped to the MPU address space from 0x8000
to 0xFFFF in 32 KB banks. When MPU address[15] = 1, the address in flash is
mapped to FL_BANK[2:0], MPU Address[14:0]. FL_BANK is reset by the erase cycle.