Datasheet
Table Of Contents
- 1 Hardware Description
- 1.1 Hardware Overview
- 1.2 Analog Front End (AFE)
- 1.3 Digital Computation Engine (CE)
- 1.4 80515 MPU Core
- 1.4.1 Memory Organization and Addressing
- 1.4.2 Special Function Registers (SFRs)
- 1.4.3 Generic 80515 Special Function Registers
- 1.4.4 Special Function Registers (SFRs) Specific to the 71M6531D/F and 71M6532D/F
- 1.4.5 Instruction Set
- 1.4.6 UARTs
- 1.4.7 Timers and Counters
- 1.4.8 WD Timer (Software Watchdog Timer)
- 1.4.9 Interrupts
- 1.5 On-Chip Resources
- 1.5.1 Oscillator
- 1.5.2 Internal Clocks
- 1.5.3 Real-Time Clock (RTC)
- 1.5.4 Temperature Sensor
- 1.5.5 Physical Memory
- 1.5.6 Optical Interface
- 1.5.7 Digital I/O – 71M6531D/F
- 1.5.8 Digital I/O – 71M6532D/F
- 1.5.9 Digital IO – Common Characteristics for 71M6531D/F and 71M6532D/F
- 1.5.10 LCD Drivers – 71M6531D/F
- 1.5.11 LCD Drivers – 71M6532D/F
- 1.5.12 LCD Drivers – Common Characteristics for 71M6531D/F and 71M6532D/F
- 1.5.13 Battery Monitor
- 1.5.14 EEPROM Interface
- 1.5.15 SPI Slave Port
- 1.5.16 Hardware Watchdog Timer
- 1.5.17 Test Ports (TMUXOUT pin)
- 2 Functional Description
- 3 Application Information
- 3.1 Connection of Sensors
- 3.2 Connecting 5-V Devices
- 3.3 Temperature Measurement
- 3.4 Temperature Compensation
- 3.5 Connecting LCDs
- 3.6 Connecting I2C EEPROMs
- 3.7 Connecting Three-Wire EEPROMs
- 3.8 UART0 (TX/RX)
- 3.9 Optical Interface (UART1)
- 3.10 Connecting the V1 Pin
- 3.11 Connecting the Reset Pin
- 3.12 Connecting the Emulator Port Pins
- 3.13 Connecting a Battery
- 3.14 Flash Programming
- 3.15 MPU Firmware
- 3.16 Crystal Oscillator
- 3.17 Meter Calibration
- 4 Firmware Interface
- 4.1 I/O RAM and SFR Map – Functional Order
- 4.2 I/O RAM Description – Alphabetical Order
- 4.3 CE Interface Description
- 5 Electrical Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 Recommended External Components
- 5.3 Recommended Operating Conditions
- 5.4 Performance Specifications
- 5.4.1 Input Logic Levels
- 5.4.2 Output Logic Levels
- 5.4.3 Power-Fault Comparator
- 5.4.4 Battery Monitor
- 5.4.5 Supply Current
- 5.4.6 V3P3D Switch
- 5.4.7 2.5 V Voltage Regulator
- 5.4.8 Low-Power Voltage Regulator
- 5.4.9 Crystal Oscillator
- 5.4.10 LCD DAC
- 5.4.11 LCD Drivers
- 5.4.12 Optical Interface
- 5.4.13 Temperature Sensor
- 5.4.14 VREF
- 5.4.15 ADC Converter, V3P3A Referenced
- 5.5 Timing Specifications
- 5.6 Typical Performance Data
- 5.7 71M6531D/F Package
- 5.8 71M6532D/F Package
- 5.9 Pin Descriptions
- 6 Ordering Information
- 7 Related Information
- 8 Contact Information
- Appendix A: Acronyms
- Appendix B: Revision History
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
Rev 2 81
Name
Location
Reset
Wake
Dir
Description
IEN_WD_NROVF
20B0[0]
0
0
R/W
Active high watchdog near overflow interrupt enable.
IE_XFER
IE_RTC
SFR E8[0]
SFR E8[1]
0
0
0
0
R/W
Interrupt flags. These flags monitor the XFER_BUSY interrupt and the RTC_1SEC
interrupt. The flags are set by hardware and clear automatically.
IE_WAKE
SFR E8[5] 0 – R/W
Indicates that the MPU was awakened by the autowake timer. This bit is typically read
by the MPU on bootup. The firmware must write a zero to this bit to clear it.
INTBITS
SFR F8[6:0]
–
– R/W
Interrupt inputs. The MPU may read these bits to see the status of external interrupts
INT0, INT1 up to INT6. These bits do not have any memory and are primarily intended
for debug use.
LCD_BITMAP
[31:24]
2023
0
L
R/W
Configuration for DIO11/SEG31 through DIO4/SEG24. Unused bits should be set to zero.
1 = LCD pin, 0 = DIO pin. Check Table 54 for bit availability.
LCD_BITMAP
[39:32]
2024
0
L
R/W
Bitmap of DIO19/SEG39 through DIO12/SEG32. Unused bits should be set to zero.
1 = LCD pin, 0 = DIO pin. Check Table 54 for bit availability.
LCD_BITMAP
[55:48]
2026 0 L R/W Bitmap of DIO28/SEG48 through DIO35/SEG55. Unused bits should be set to zero.
1 = LCD pin, 0 = DIO pin. Check Table 54 for bit availability.
LCD_BITMAP
[63:56]
2027
0
L
R/W
Bitmap of DIO36/SEG56 through DIO43/SEG63. Unused bits should be set to zero.
1 = LCD pin, 0 = DIO pin. Check Table 54 for bit availability.
LCD_BITMAP
[71:64]
2028
0
L
R/W
Bitmap of DIO44/SEG64 through DIO51/SEG71. Unused bits should be set to zero.
1 = LCD pin, 0 = DIO pin. Check Table 54 for bit availability.
LCD_BLKMAP19
[3:0]
LCD_BLKMAP18
[3:0]
205A[7:4]
205A[3:0]
0
L
R/W
Identifies which segments connected to SEG18 and SEG19 should blink. 1 means
blink. The most significant bit corresponds to COM3, the least significant bit to COM0.
LCD_CLK[1:0]
2021[1:0] 0 L R/W
Sets the LCD clock frequency for COM/SEG pins (not frame rate) according to the
following (f
w
= 32768 Hz):
00 = f
w
/2
9
01 = f
w/
2
8
10 = f
w
/2
7
11 = f
w
/2
6