Datasheet

Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005
84 Rev 2
Name
Location
Reset
Wake
Dir
Description
MUX_ALT
2005[2] 0 0 R/W
The MPU asserts this bit when it wishes the MUX to perform ADC conversions on an
alternate set of inputs.
If CHOP_E[1:0] is 00, MUX_ALT is automatically asserted once per sumcycle, when
XFER_BUSY falls.
MUX_DIV[3:0]
209D[3:0]
0
0
R/W
The number of states in the input multiplexer.
MUX_SYNC_E
2020[7]
0
0
R/W
When set, SEG7 outputs MUX_SYNC. Otherwise, SEG7 is an LCD pin.
OPT_FDC[1:0]
2007[1:0] 0 0 R/W
Selects the modulation duty cycle for OPT_TX.
OPT_FDC[1:0]
Function
00
50% Low
01
25% Low
10
12.5% Low
11
6.25% Low
OPT_RXDIS
2008[5] 0 0 R/W
Configures OPT_RX to an analog input to the optical UART comparator or as a digital
input/output, DIO1: 0 = OPT_RX, 1 = DIO1.
OPT_RXINV
2008[4] 0 0 R/W
Inverts the result from the OPT_RX comparator when 1. Affects only the UART input.
Has no effect when OPT_RX is used as a DIO input.
OPT_TXE[1:0]
2007[7:6] 00 00 R/W
Configures the OPT_TX output pin.
OPT_TXE[1:0]
Function
00
OPT_TX
01
DIO2
10
WPULSE
11
RPULSE
OPT_TXINV
2008[0]
0
0
R/W
Inverts OPT_TX when 1. This inversion occurs before modulation.
OPT_TXMOD
2008[1] 0 0 R/W
Enables modulation of OPT_TX. When
OPT_TXMOD
is set, OPT_TX is modulated
when it would otherwise have been zero. The modulation is applied after any inversion
caused by OPT_TXINV.
PLL_OK
2003[6]
0
0
R
Indicates that system power is present and the clock generation PLL is settled.
PLS_MAXWIDTH
[7:0]
2080[7:0] FF FF R/W
Determines the maximum width of the pulse (low going pulse).
The maximum pulse width is (2*PLS_MAXWIDTH + 1)*T
I
. Where T
I
is PLS_INTERVAL
.
If PLS_INTERVAL = 0, T
I
is the sample time (397 µs). If set to 255, pulse width control
is disabled and pulses are output with a 50% duty cycle.
PLS_INTERVAL
[7:0]
2081[7:0] 0 0 R/W
For PULSE_W and PULSE_V only: If the FIFO is used, PLS_INTERVAL must be set to
81. If PLS_INTERVAL = 0, the FIFO is not used and pulses are output as soon as the
CE issues them.