Datasheet

FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
Rev 2 85
Name
Location
Reset
Wake
Dir
Description
PLS_INV
2004[6] 0 0 R/W
Inverts the polarity of the pulse outputs. Normally, these pulses are active low. When
inverted, they become active high.
PREBOOT
SFRB2[7]
–
–
R
Indicates that the preboot sequence is active.
PREG[16:0]
201C[2:0]
201D[7:0]
201E[7:2]
4
0
0
NV
NV
NV
R/W
R/W
R/W
RTC adjust. See Section 1.5.3 Real-Time Clock (RTC) for additional details.
0x0FFBF ≤ PREG[16:0] ≤ 0x10040
PREG[16:0] and QREG[1:0] are separate in hardware but can be programmed with a
single number calculated by the MPU. PREG[16:0] and QREG[1:0] are non-volatile, but
have no correcting function in SLEEP mode.
PRE_SAMPS[1:0]
2001[7:6] 0 0 R/W
The duration of the pre-summer, in samples.
PRE_SAMPS[1:0]
Pre-summer Duration
00
42
01
50
10
84
11
100
QREG[1:0]
201E[1:0]
0
0
R/W
RTC adjust. See Section 1.5.3 Real-Time Clock (RTC) for additional details.
RST_SUBSEC
2010[0]
0
0
R/W
The sub-second counter is restarted when a 1 is written to this bit.
RTCA_ADJ[6:0]
2011[6:0]
40
–
R/W
Analog RTC adjust. See Section 1.5.3 Real-Time Clock (RTC) for additional details.
RTC_SEC[5:0
RTC_MIN[5:0]
RTC_HR[4:0]
RTC_DAY[2:0]
RTC_DATE[4:0]
RTC_MO[3:0]
RTC_YR[7:0]
2015
2016
2017
2018
2019
201A
201B
*
*
*
*
*
*
*
NV
NV
NV
NV
NV
NV
NV
R/W
These are the year, month, day, hour, minute and second parameters of the RTC.
Writing to these registers sets the time. Each write operation to one of these registers
must be preceded by a write to 0x201F (WE). Valid values for each parameter are:
SEC: 00 to 59, MIN: 00 to 59, HR: 00 to 23 (00 = Midnight)
DAY: 01 to 07 (01 = Sunday), DATE: 01 to 31, MO: 01 to 12
YR: 00 to 99 (00 and all others divisible by 4 are leap years)
Values in the RTC registers are undefined when the IC powers up without a battery but
are maintained through mission and battery modes when a sufficient voltage is maintained
at the VBAT pin.
* no change of value at reset. See Application Note AN4947 for details on RTC.
RTM_E
2002[3]
0
0
R/W
Real Time Monitor (RTM) enable. When 0, the RTM output is low.
RTM0[9:0]
RTM1[9:0]
RTM2[9:0]
RTM3[9:0]
2060[9:8]
2061[7:0]
2062[9:8]
2063[7:0]
2064[9:8]
2064[7:0]
2065[9:8]
2066[7:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
The four RTM probes. Before each CE code pass, the values of these registers are
serially output on the RTM pin. The RTM registers are ignored when RTM_E = 0.