Datasheet

Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005
86 Rev 2
Name
Location
Reset
Wake
Dir
Description
SECURE
SFRB2[6] 0 – R/W
When set, enables security provisions that prevent external reading of the flash memory
(zeros will be returned if the flash is read). SECURE should be set during the preboot
phase, i.e. while PREBOOT is set. SECURE is cleared when the flash is mass-erased
and when the chip is reset. The bit may only be set, attempts to write zero are ignored.
SEL_IAN
20AC[1] 0 0 R/W
When set to 1, selects differential mode for the current input (IAP, IAN). When 0, the
input remains single-ended (71M6532D/F only).
SEL_IBN
20AC[5] 0 0 R/W
When set to 1, selects differential mode for the current input (IBP, IBN). When 0, the
input remains single-ended (71M6532D/F only).
SLEEP
20A9[6] 0 0 W
Puts the 71M6531 into SLEEP mode. This bit is ignored if system power is present.
The 71M6531 will wake when the autowake timer times out, when the push button is
pushed, when system power returns, or when RESET goes high.
SLOT0_SEL[3:0]
SLOT1_SEL[3:0]
SLOT2_SEL[3:0]
SLOT3_SEL[3:0]
2090[3:0]
2090[7:4]
2091[3:0]
2091[7:4]
0
1
2
3
0
1
2
3
R/W
Primary multiplexer frame analog input selection. These bits map the selected input,
0-3 to the multiplexer state. The ADC output is always written to the memory location
corresponding to the input, regardless of which multiplexer state an input is mapped to
(see Section 1.2 Analog Front End (AFE)).
SLOT0_ALTSEL
[3:0]
SLOT1_ALTSEL
[3:0]
SLOT2_ALTSEL
[3:0]
SLOT3_ALTSEL
[3:0]
2096[3:0]
2096[7:4]
2097[3:0]
2097[7:4]
A
1
2
3
A
1
B
3
R/W
Alternate multiplexer frame analog input selection. Maps the selected input to the
multiplexer state.
The additional inputs, 10 and 11 in the alternate frame are:
10 = TEMP
11 = VBAT
SP_ADDR[15:8]
SP_ADDR[7:0]
2072[7:0]
2073[7:0]
0
0
0
0
R
R
SPI Address. 16-bit address from the bus master.
SP_CMD
2071
0
0
R
SPI command. 8-bit command from the bus master.
SPE
2070[7]
0
0
R/W
SPI port enable. Enables the SPI interface on pins SEG3 through SEG5.
SPI_FLAG
20B1[4] 1 1 R/W
SPI interrupt flag. The flag is set by the hardware and is cleared by the firmware writing
a 0. Firmware using this interrupt should clear the spurious interrupt indication during
initialization.
SUBSEC[7:0]
2014[7:0]
– –
R
The remaining count, in terms of 1/256 RTC cycles, to the next one second boundary.
SUBSEC may be read by the MPU after the one second interrupt and before reaching
the next one second boundary. Setting RST_SUBSEC will clear SUBSEC.
SUM_CYCLES
[5:0]
2001[5:0] 0 0 R/W The number of pre-summer outputs summed in the final summing stage of the CE.
TMUX[4:0]
20AA[4:0] 2 – R/W
Selects one of 32 signals for TMUXOUT. For details, see Section 1.5.17 Test Ports
(TMUXOUT pin).
TRIM[7:0]
20FF
0
0
R/W
Contains fuse information, depending on the value written to TRIMSEL[3:0].