Datasheet
Table Of Contents
- 1 Hardware Description
- 1.1 Hardware Overview
- 1.2 Analog Front End (AFE)
- 1.3 Digital Computation Engine (CE)
- 1.4 80515 MPU Core
- 1.4.1 Memory Organization and Addressing
- 1.4.2 Special Function Registers (SFRs)
- 1.4.3 Generic 80515 Special Function Registers
- 1.4.4 Special Function Registers (SFRs) Specific to the 71M6531D/F and 71M6532D/F
- 1.4.5 Instruction Set
- 1.4.6 UARTs
- 1.4.7 Timers and Counters
- 1.4.8 WD Timer (Software Watchdog Timer)
- 1.4.9 Interrupts
- 1.5 On-Chip Resources
- 1.5.1 Oscillator
- 1.5.2 Internal Clocks
- 1.5.3 Real-Time Clock (RTC)
- 1.5.4 Temperature Sensor
- 1.5.5 Physical Memory
- 1.5.6 Optical Interface
- 1.5.7 Digital I/O – 71M6531D/F
- 1.5.8 Digital I/O – 71M6532D/F
- 1.5.9 Digital IO – Common Characteristics for 71M6531D/F and 71M6532D/F
- 1.5.10 LCD Drivers – 71M6531D/F
- 1.5.11 LCD Drivers – 71M6532D/F
- 1.5.12 LCD Drivers – Common Characteristics for 71M6531D/F and 71M6532D/F
- 1.5.13 Battery Monitor
- 1.5.14 EEPROM Interface
- 1.5.15 SPI Slave Port
- 1.5.16 Hardware Watchdog Timer
- 1.5.17 Test Ports (TMUXOUT pin)
- 2 Functional Description
- 3 Application Information
- 3.1 Connection of Sensors
- 3.2 Connecting 5-V Devices
- 3.3 Temperature Measurement
- 3.4 Temperature Compensation
- 3.5 Connecting LCDs
- 3.6 Connecting I2C EEPROMs
- 3.7 Connecting Three-Wire EEPROMs
- 3.8 UART0 (TX/RX)
- 3.9 Optical Interface (UART1)
- 3.10 Connecting the V1 Pin
- 3.11 Connecting the Reset Pin
- 3.12 Connecting the Emulator Port Pins
- 3.13 Connecting a Battery
- 3.14 Flash Programming
- 3.15 MPU Firmware
- 3.16 Crystal Oscillator
- 3.17 Meter Calibration
- 4 Firmware Interface
- 4.1 I/O RAM and SFR Map – Functional Order
- 4.2 I/O RAM Description – Alphabetical Order
- 4.3 CE Interface Description
- 5 Electrical Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 Recommended External Components
- 5.3 Recommended Operating Conditions
- 5.4 Performance Specifications
- 5.4.1 Input Logic Levels
- 5.4.2 Output Logic Levels
- 5.4.3 Power-Fault Comparator
- 5.4.4 Battery Monitor
- 5.4.5 Supply Current
- 5.4.6 V3P3D Switch
- 5.4.7 2.5 V Voltage Regulator
- 5.4.8 Low-Power Voltage Regulator
- 5.4.9 Crystal Oscillator
- 5.4.10 LCD DAC
- 5.4.11 LCD Drivers
- 5.4.12 Optical Interface
- 5.4.13 Temperature Sensor
- 5.4.14 VREF
- 5.4.15 ADC Converter, V3P3A Referenced
- 5.5 Timing Specifications
- 5.6 Typical Performance Data
- 5.7 71M6531D/F Package
- 5.8 71M6532D/F Package
- 5.9 Pin Descriptions
- 6 Ordering Information
- 7 Related Information
- 8 Contact Information
- Appendix A: Acronyms
- Appendix B: Revision History
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
Rev 2 87
Name
Location
Reset
Wake
Dir
Description
TRIMSEL[3:0]
20FD[3:0] 0 0 R/W
Selects the trim fuse to be read with the TRIM register:
TRIMSEL[3:0]
Trim Fuse
Purpose
1
TRIMT[7:0]
Trim for the magnitude of VREF
VERSION[7:0]
2006
20C8
–
–
–
–
R
R
The device version index. This word may be read by the firmware to determine the
silicon version.
VERSION[7:0]
Silicon Version
0001 0101
A05
VREF_CAL
2004[7]
0
0
R/W
Brings VREF to the VREF pad. This feature is disabled when VREF_DIS =1.
VREF_DIS
2004[3]
0
0
R/W
Disables the internal voltage reference.
WAKE_ARM
20A9[7] 0 – W
Arm the autowake timer. Writing a 1 to this bit arms the autowake timer and presets it
with the values presently in WAKE_PRD and WAKE_RES. The autowake timer is reset and
disarmed whenever the IC is in MISSION or BROWNOUT mode. The timer must be
armed at least three RTC cycles before the SLEEP or LCD-ONLY mode is commanded.
WAKE_PRD
20A9[2:0]
001
–
R/W
Sleep time. Time = WAKE_PRD[2:0]*WAKE_RES. Default = 001. Maximum value is 7.
WAKE_RES
20A9[3]
0
–
R/W
Resolution of WAKE timer: 1 = 1 minute, 0 = 2.5 seconds.
WD_NROVF_
FLAG
20B1[0]
–
0
R/W
This flag is set approximately 1 ms before the watchdog timer overflows. It is cleared
by writing a 0 or on the falling edge of WAKE.
WD_RST
SFR F8[7] 0 0 W
WD timer bit. This bit must be accessed with byte operations. Operations possible for
this bit are: Write 0xFF: Resets the WDT.
WD_OVF
2002[2] 0 0 R/W
The WD overflow status bit. This bit is set when the WD timer overflows. It is powered
by the nonvolatile supply and at bootup will indicate if the part is recovering from a WD
overflow or a power fault. This bit should be cleared by the MPU on bootup. It is also
automatically cleared when RESET is high.
*Not preserved in SLEEP mode
WE
201F[7:0]
–
–
W
An 8-bit value has to be written to this address prior to accessing the RTC registers.
WRPROT_BT
SFR B2[5] 0 0
When set, this bit protects flash addresses from 0 to BOOT_SIZE*1024 from flash page
erase.
WRPROT_CE
SFR B2[4] 0 0
When set, this bit protects flash addresses from CE_LCTN*1024 to the end of memory
from flash page erase.