Datasheet

FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
Rev 2 89
• Select the values for SLOT0_SEL[3:0] = 0, SLOT1_SEL[3:0] = 1, SLOT2_SEL[3:0] = 2, SLOT3_SEL[3:0]
= 3
• Select the values for SLOT0_ALTSEL[3:0] = 0x0A, SLOT1_ALTSEL[3:0] = 1, SLOT2_ALTSEL[3:0] =
0x0B, SLOT3_ALTSEL[3:0] = 3.
• Set CHOP_E[1:0] = 00.
• Initialize any MPU interrupts, such as CE_BUSY, XFER_BUSY, or a power failure detection interrupt.
When different CE codes are used, a different set of environment parameters needs to be established.
The exact values for these parameters are stated in the Application Notes and other documentation
accompanying the CE codes.
CE codes should only be used with environment parameters specified in this document or in the
applicable CE code description. Changing environment parameters at random will lead to unpre-
dictable results.
Typically, there are thirteen 32768 Hz cycles per ADC multiplexer frame (see Figure 19). This means that
the product of the number of cycles per frame and the number of conversions per frame must be 12 (allowing
for one settling cycle).
During operation, CHOP_E[1:0] = 00 enables the automatic chopping mode and forces an alternate
multiplexer sequence at regular intervals. This enables accurate temperature measurement.
4.3.5 CE Calculations
Table 56: CE EQU[2:0] Equations and Element Input Mapping
EQU[2:0]
Watt & VAR Formula
(WSUM/VARSUM)
Element Input Mapping
W0SUM/
VAR0SUM
W1SUM/
VAR1SUM
I0SQSUM I1SQSUM
0
VA IA (1 element, 2W 1φ)
with tamper detection
VA*IA VA*IB IA IB
1
VA*(IA-IB)/2
(1 element, 3W 1
φ
)
VA*(IA-IB)/2 (VA * IB)/2 IA-IB IB
2
VA*IA + VB*IB
(2 element, 4W 2φ)
VA*IA VB*IB IA IB
4.3.6 CE Status and Control
The CESTATUS register provides information about the status of voltage and input AC signal frequency,
which are useful for generating early power fail warnings, e.g. to initiate necessary data storage. It contains
sag warning flags for VA and VB as well as F
0
, the derived clock operating at the fundamental input
frequency. CESTATUS represents the status flags for the preceding CE code pass (CE busy interrupt).
Sag alarms are not remembered from one code pass to the next. The CE Status word is refreshed at
every CE_BUSY interrupt. The significance of the bits in CESTATUS is shown in Table 57.
CE Address
Name
Description
0x80
CESTATUS
See description of CESTATUS bits in Table 57.
Since the CE_BUSY interrupt typically occurs at 2520.6 Hz, it is desirable to minimize the computation
required in the interrupt handler of the MPU. Rather than reading the CE status word at every CE_BUSY
interrupt and interpret the sag bits, it is recommended that the MPU activate the YPULSE output to generate
interrupts when a sag occurs (see the description of the CECONFIG register)