Datasheet
Table Of Contents
- 1 Hardware Description
- 1.1 Hardware Overview
- 1.2 Analog Front End (AFE)
- 1.3 Digital Computation Engine (CE)
- 1.4 80515 MPU Core
- 1.4.1 Memory Organization and Addressing
- 1.4.2 Special Function Registers (SFRs)
- 1.4.3 Generic 80515 Special Function Registers
- 1.4.4 Special Function Registers (SFRs) Specific to the 71M6531D/F and 71M6532D/F
- 1.4.5 Instruction Set
- 1.4.6 UARTs
- 1.4.7 Timers and Counters
- 1.4.8 WD Timer (Software Watchdog Timer)
- 1.4.9 Interrupts
- 1.5 On-Chip Resources
- 1.5.1 Oscillator
- 1.5.2 Internal Clocks
- 1.5.3 Real-Time Clock (RTC)
- 1.5.4 Temperature Sensor
- 1.5.5 Physical Memory
- 1.5.6 Optical Interface
- 1.5.7 Digital I/O – 71M6531D/F
- 1.5.8 Digital I/O – 71M6532D/F
- 1.5.9 Digital IO – Common Characteristics for 71M6531D/F and 71M6532D/F
- 1.5.10 LCD Drivers – 71M6531D/F
- 1.5.11 LCD Drivers – 71M6532D/F
- 1.5.12 LCD Drivers – Common Characteristics for 71M6531D/F and 71M6532D/F
- 1.5.13 Battery Monitor
- 1.5.14 EEPROM Interface
- 1.5.15 SPI Slave Port
- 1.5.16 Hardware Watchdog Timer
- 1.5.17 Test Ports (TMUXOUT pin)
- 2 Functional Description
- 3 Application Information
- 3.1 Connection of Sensors
- 3.2 Connecting 5-V Devices
- 3.3 Temperature Measurement
- 3.4 Temperature Compensation
- 3.5 Connecting LCDs
- 3.6 Connecting I2C EEPROMs
- 3.7 Connecting Three-Wire EEPROMs
- 3.8 UART0 (TX/RX)
- 3.9 Optical Interface (UART1)
- 3.10 Connecting the V1 Pin
- 3.11 Connecting the Reset Pin
- 3.12 Connecting the Emulator Port Pins
- 3.13 Connecting a Battery
- 3.14 Flash Programming
- 3.15 MPU Firmware
- 3.16 Crystal Oscillator
- 3.17 Meter Calibration
- 4 Firmware Interface
- 4.1 I/O RAM and SFR Map – Functional Order
- 4.2 I/O RAM Description – Alphabetical Order
- 4.3 CE Interface Description
- 5 Electrical Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 Recommended External Components
- 5.3 Recommended Operating Conditions
- 5.4 Performance Specifications
- 5.4.1 Input Logic Levels
- 5.4.2 Output Logic Levels
- 5.4.3 Power-Fault Comparator
- 5.4.4 Battery Monitor
- 5.4.5 Supply Current
- 5.4.6 V3P3D Switch
- 5.4.7 2.5 V Voltage Regulator
- 5.4.8 Low-Power Voltage Regulator
- 5.4.9 Crystal Oscillator
- 5.4.10 LCD DAC
- 5.4.11 LCD Drivers
- 5.4.12 Optical Interface
- 5.4.13 Temperature Sensor
- 5.4.14 VREF
- 5.4.15 ADC Converter, V3P3A Referenced
- 5.5 Timing Specifications
- 5.6 Typical Performance Data
- 5.7 71M6531D/F Package
- 5.8 71M6532D/F Package
- 5.9 Pin Descriptions
- 6 Ordering Information
- 7 Related Information
- 8 Contact Information
- Appendix A: Acronyms
- Appendix B: Revision History
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F
Rev 2 91
Table 58: CECONFIG Bit Definitions
CECONFG
[bit]
Name Default Description
[19]
[18]
SAG_MASK1
SAG_MASK0
0
0
Sets the sag control of phase B.
Sets the sag control of phase A.
If more than one sag mask is set, a sag interrupt will only be
generated when all phases enabled for the interrupt sag.
[17]
SAG_INT
0
When set, enables the sag interrupt to be output on the
YPULSE/DIO9 pin.
[16]
EXT_TEMP
0
When set, enables the control of GAIN_ADJ by the MPU.
When 0, enables the control of GAIN_ADJ by the CE.
[15:8]
SAG_CNT
80
(0x50)
The number of consecutive voltage samples below SAG_THR
before a sag alarm is declared. The maximum value is 255.
SAG_THR
is at address 0x24.
[7]
FREQSEL1
0
The combination of FREQSEL1 and FREQSEL0 selects the phase
to be used for the frequency monitor, the phase-to-phase lag
calculation, the zero-crossing counter MAINEDGE_X and the
F0 bit (CESTATUS[28]).
FREQSEL1/FREQSEL0 = 0/0: Phase A
FREQSEL1
/
FREQSEL0
= 0/1: Phase B
[6]
FREQSEL0
0
[5]
EXT_PULSE
1
When zero, causes the pulse generators to respond to internal
data (PULSE0 = WSUM_X, PULSE1 = VARSUM_X., PULSE2 =
VASUM_X). Otherwise, the generators respond to values the
MPU places in APULSEW and APULSER.
[4] – 0 Unused.
[3]
IB_SHUNT
0
When 1, the current gain of channel B is increased by 8. The
gain factor controlled by In_SHUNT is referred to as In_8
throughout this document.
[2]
IA_SHUNT
0
When 1, the current gain of channel A is increased by 8.
[1]
PULSE_FAST
0
When PULSE_FAST = 1, the pulse generator input is increased
16x. When PULSE_SLOW = 1, the pulse generator input is
reduced by a factor of 64. These two bits control the pulse
gain factor X (see table below). Default is 0 for both (X = 6).
PULSE_SLOW
PULSE_FAST
X
0
0
1.5 * 2
2
= 6
0
1
1.5 * 2
6
= 96
1
0
1.5 * 2
-4
= 0.09375
1
1
Do not use
[0]
PULSE_SLOW
0
Table 59: Sag Threshold Control
CE
Address
Name Default Description
0x24
SAG_THR
443000
The threshold for sag warnings. The default value is
equivalent to 80 V RMS if VMAX = 600 V. The LSB value
is VMAX * 4.255*10
-7
V (peak).
Table 60: Gain Adjust Control
CE
Address
Name Default Description
0x40
GAIN_ADJ
16384
This register scales all voltage and current channels. The
default value is equivalent unity gain (1.000).