Datasheet

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet
Rev 2 117
6.5.5 SPI Slave Port (MISSION Mode)
Table 90: SPI Slave Port (MISSION Mode) Timing
Parameter
Condition
Min
Typ
Max
Unit
t
SPIcyc
PCLK cycle time
1
µs
t
SPILead
Enable lead time
15
ns
t
SPILag
Enable lag time
0
ns
t
SPIW
PCLK pulse width:
High
Low
40
40
ns
ns
t
SPISCK
PCSZ to first PCLK fall
Ignore if PCLK is low
when PCSZ falls.
2 ns
t
SPIDIS
Disable time
0
ns
t
SPIEV
PCLK to Data Out
15
ns
t
SPISU
Data input setup time
10
ns
t
SPIH
Data input hold time
5
ns
MSB OUT
LSB OUT
MSB IN
LSB IN
t
SPIcyc
t
SPILead
t
SPILag
t
SPISCK
t
SPIH
t
SPIW
t
SPIEV
t
SPIW
t
SPIDIS
PCSZ
PCLK
PSDI
PSDO
Figure 48: SPI Slave Port (MISSION Mode) Timing