Datasheet
71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004
44 Rev 2
Table 41: Data/Direction Registers and Internal Resources for DIO 36-47
DIO
–
–
–
–
36*
37*
38*
39*
–
41
42*
43
44
45
46*
47
LCD Segment
–
–
–
–
56*
57*
58*
59*
–
61
62*
63
64
65
66*
67
71M6533 Pin #
–
–
–
–
–
–
–
–
–
99
–
40
31
38
–
22
71M6534 Pin #
–
–
–
–
87
88
89
90
–
117
118
46
37
44
5
27
Configuration (DIO
or LCD segment)
–
–
–
–
0*
1*
2*
3*
–
5
6*
7
0
1
2*
3
LCD_BITMAP[55:48]
LCD_BITMAP[63:56]
LCD_BITMAP[71:64]
Data Register
– – – –
LCD_SEG56[0]*
LCD_SEG57[0]*
LCD_SEG58[0]*
LCD_SEG59[0]*
–
LCD_SEG61[0]
LCD_SEG62[0]*
LCD_SEG63[0]
LCD_SEG64[0]
LCD_SEG65[0]
LCD_SEG66[0]*
LCD_SEG67[0]
Direction Register
0 = input, 1 = output
– – – –
LCD_SEG56[3]*
LCD_SEG57[3]*
LCD_SEG58[3]*
LCD_SEG59[3]*
LCD_SEG61[3]
LCD_SEG62[3]*
LCD_SEG63[3]
LCD_SEG64[3]
LCD_SEG65[3]
LCD_SEG66[3]*
LCD_SEG67[3]
Table 42: Data/Direction and Internal Resources for DIO 48-58
DIO
48
49
50
51
52*
53*
54*
55*
56
57
58
LCD Segment
68
69
70
71
72*
73*
74*
75*
–
–
–
71M6533 Pin #
23
24
25
50
–
–
–
–
14
15
16
71M6534 Pin #
28
29
30
56
57
58
59
60
19
20
21
Configuration (DIO
or LCD segment)
4
5
6
7
0*
1*
2*
3*
Always DIO
LCD_BITMAP[71:64]
LCD_BITMAP[80:72]
Data Register
LCD_SEG68[0]
LCD_SEG69[0]
LCD_SEG70[0]
LCD_SEG71[0]
LCD_SEG72[0]*
LCD_SEG73[0]*
LCD_SEG74[0]*
LCD_SEG75[0]*
DIO_56[4]
DIO_57[4]
DIO_58[4]
Direction Register
0 = input, 1 = output
LCD_SEG68[3]
LCD_SEG69[3]
LCD_SEG70[3]
LCD_SEG71[3]
LCD_SEG72[3]*
LCD_SEG73[3]*
LCD_SEG74[3]*
LCD_SEG75[3]*
DIO_DIR56[7]
DIO_DIR57[7]
DIO_DIR58[7]
See the tables in the I/O RAM Description (Section 5.2) for exact bit locations. For example,
DIO43 is controlled by LCD_SEG63[0] which resolves to I/O RAM location 0x2045[4].
DIO24 and higher do not have SFR registers for direction control. DIO36 and higher do not have SFR
registers for data access. The direction control of these pins is achieved with the LCD_SEGn[3] registers
and data access is controlled with the LCD_SEGn[0] registers in I/O RAM. DIO56 through DIO58 are
dedicated DIO pins. They are controlled with DIO_DIR56[7] through DIO_DIR58[7] (direction) and with
DIO_56[4] through DIO_58[4] (data) in I/O RAM.