Datasheet

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004
94 Rev 2
VERSION[7:0]
2006
20C8
–
–
–
–
R
R
The device version index. This word may be read by the firmware to determine the
silicon version.
VERSION[7:0]
Silicon Version
0000 0101
A05
VREF_CAL
2004[7]
0
0
R/W
Brings VREF to the VREF pad. This feature is disabled when VREF_DIS =1.
VREF_DIS
2004[3]
0
0
R/W
Disables the internal voltage reference.
WAKE_ARM
20A9[7] 0
–
W
Writing a 1 to this bit arms the autowake timer and presets it with the values presently
in WAKE_PRD and WAKE_RES. The autowake timer is reset and disarmed whenever
the processor is in MISSION mode or BROWNOUT mode. The timer must be armed
at least three RTC cycles before the SLEEP or LCD-ONLY mode is commanded.
WAKE_PRD
20A9[2:0] 001
–
R/W
Sleep time. Time = WAKE_PRD[2:0]*WAKE_RES. The default = 001. The maximum
value is 7.
WAKE_RES
20A9[3]
0
–
R/W
Resolution of WAKE timer: 1 = 1 minute, 0 = 2.5 seconds.
WD_NROVF_
FLAG
20B1[0] – 0 R/W
This flag is set approximately 1 ms before the watchdog timer overflows. It is cleared
by writing a 0 or on the falling edge of WAKE.
WD_RST
SFR F8[7] 0 0 W
WD timer bit. This bit must be accessed with byte operations. Operations possible for
this bit are:
Write 0: Clears the flag.
Write 1: Resets the WDT.
WD_OVF
2002[2] 0 NV* R/W
The WDT overflow status bit, set when the WDT overflows. It is preserved in LCD
mode and will indicate at bootup if the part is recovering from a WDT overflow or a
power fault. This bit should be cleared by the MPU on bootup. It is also automatically
cleared when RESET is high.
*Not preserved in SLEEP mode
WE
201F[7:0]
W
An 8-bit value has to be written to this address prior to accessing the RTC registers.
WRPROT_BT
SFR B2[5]
0
0
When set, this bit protects flash addresses from 0 to BOOT_SIZE*1024 from flash page erase.
WRPROT_CE
SFR B2[4] 0 0
When set, this bit protects flash addresses from CE_LCTN*1024 to the end of memory
from flash page erase.
†
Applicable to the 71M6534 only.