Datasheet

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet
Rev 2 97
5.3.5 CE Calculations
Table 55: CE EQU[2:0] Equations and Element Input Mapping
EQU[
2:0]
Watt & VAR
Formula
(WSUM/VARS
UM)
Element Input Mapping
W0SUM/ VAR0SUM
W1SUM/
VAR1SUM
W2SUM/
VAR2SUM
I0SQ
SUM
I1SQ
SUM
I2SQ
SUM
0*
VA IA
(1 element, 2W
1
φ
)
VA*IA
– –
IA
– –
1*
VA*(IA-IB)/2
(1 element, 3W
1
φ
)
VA*(IA-IB)/2
– –
IA-IB IB
–
2*
VA*IA + VB*IB
(2 element, 3W
3
φ
Delta)
VA*IA VB*IB
–
IA IB
–
3*
VA*(IA-IB)/2 +
VC*IC
(2 element, 4W
3
φ
Delta)
VA*(IA-IB)/2
–
VC*IC IA-IB IB IC
4*
VA*(IA-IB)/2 +
VB*(IC-IB)/2
(2 element, 4W
3
φ
Wye)
VA*(IA-IB)/2 VB*(IC-IB)/2
–
IA-IB IC-IB IC
5
VA*IA + VB*IB
+ VC*IC
(3 element, 4W
3
φ
Wye)
VA*IA VB*IB VC*IC IA IB IC
* Only EQU = 5 is supported by CE code version CE34A02D.
5.3.6 CE Front End Data (Raw Data)
Access to the raw data provided by the AFE is possible by reading addresses 0 through B as shown in
Table 56.
Table 56: CE Raw Data Access Locations
Name
Address
Description
CE
MPU
Type
IA FIR data
0x00
0x00
Input
ADC Input data, valid at the end of the MUX
frame. The address mapping of analog
inputs to memory is hard-wired in the ADC
converter circuit.
VA FIR data 0x01 0x04 Input
IB FIR data
0x02
0x08
Input
VB FIR data
0x03
0x0C
Input
IC FIR data
0x04
0x10
Input
VC FIR data
0x05
0x14
Input
ID FIR data
0x06
0x18
Input
TEMP FIR data
0x0A
0x28
Input
VBAT FIR data
0x0B
0x2C
Input
…
…
Internal
…
Chip ID, Version bytes 0x0F 003C
Read
Only
Upper 16 bits are zero. Lower 16 bits are
CHIP_ID[15:8], VERSION[7:0]. This word is
read only.
…
Internal
…
Last Address
0x3FF
0xFFC
Internal
Last Memory Location