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71M6533/G/

H and 71M6534/H

Energy Meter ICs

DATA SHEET

Rev 2 1

GENERAL DESCRIPTION

The Teridian™ 71M6533 and 71M6534 are third-generation

polyphase metering systems-on-chips (SoCs) with a 10MHz 8051-

compatible MPU core, low-power RTC, flash, and LCD driver. The

Single Converter Technology® with a 22-bit delta-sigma ADC, seven

analog inputs, digital temperature compensation, precision voltage

reference, and a 32-bit computation engine (CE) supports a wide

range of metering applications with very few external components.

The 71M6533 and 71M6534 add several new features to the

Teridian flagship 71M6513 polyphase meters, including an SPI

interface, advanced power management with < 1µA sleep current,

4KB shared RAM, and 128KB (71M6533/H, 71M6534), or 256KB

(71M6533G, 71M6534H) flash, which can be programmed in the

field with new code and/or data during meter operation. Higher

processing and sampling rates and larger memory offer a

powerful metering platform for commercial and industrial meters

with up to class 0.2 accuracy.

A complete array of ICE and development tools, programming

libraries and reference designs enable rapid development and

certification of meters that meet all ANSI and IEC electricity metering

standards worldwide.

FEATURES

• Wh Accuracy < 0.1% Over 2000:1 Range

• Exceeds IEC 62053/ANSI C12.20 Standards

• Seven Sensor Inputs with Neutral Current

Measurement

• Low-Jitter Wh and VARh Plus Two Additional

Pulse Test Outputs (4 Total, 10kHz max) with

Pulse Count

• Four-Quadrant Metering

• Phase Sequencing

• Line Frequency Count for RTC

• Digital Temperature Compensation

• Independent 32-Bit CE

• 46-64 Hz Line Frequency Range with Same

Calibration; Phase Compensation (± 7°)

• Three Battery-Backup Modes with Wake-Up

on Timer or Pushbutton:

Brownout Mode (82µA typ, 71M6533)

LCD Mode (21µA typ, DAC active)

Sleep Mode (0.7µA typ)

• Energy Display During Mains Power Failure

• 39mW (typ) Consumption at 3.3V, MPU

Clock Frequency 614kHz

• 8-Bit MPU (80515), 10MHz (max), One

Clock Cycle per Instruction with Integrated

ICE for Debug

• LCD Driver with Four Common Segment

Drivers:

Up to 228 Pixels (71M6533) or 300 Pixels

(71M6534)

• Four Dedicated + 35 (71M6533) or 48

(71M6534) Multifunction DIO Pins

• RTC for TOU Functions with Clock-Rate Adjust

• Hardware Watchdog Timer, Power-Fail Monitor

• I

C/MICROWIRE® EEPROM Interface

• High-Speed Slave SPI Interface to Data RAM

• Two UARTs for IR and AMR, IR Driver with

Modulation

• Flash Memory with Security and In-System

Program Update:

128KB (71M6533/H, 71M6534)

256KB (71M6533G, 71M6534H)

• 4KB RAM

• Industrial Temperature Range

• 100-Pin (71M6533/G/H) or 120-Pin

(71M6534/H) Lead(Pb)-Free LQFP Package

MPU

RTC

TIMERS

XIN

XOUT

COM0..3

V3P3A V3P3SYS

VBAT

V2P5

SEG

GNDA GNDD

SEG/DIO

DIO

ICE

LIVE

NEUT

LOAD

8888.8888

PULSES,

DIO

POWER

FAULT

AMR

COMPARATOR

MOD

SERIAL PORTS

OSC/PLL

CONVERTER

LCD DRIVER

DIO , PULSE

COMPUTE

ENGINE

FLASH

RAM

32 kHz

REGULATOR

CT / COIL

POWER SUPPLY

TERIDIAN

71M6533

71M6534

TEMP

SENSOR

VREF

BATTERY

PWR MODE

CONTROL

WAKE-up

NEUTRAL

C or µWire

EEPROM

9/24/2008

V2*

* 71M6534 only

Teridian is a trademark and Single Converter Technology is a registered

trademark of Maxim Integrated Products, Inc.

MICROWIRE is a registered trademark of National Semiconductor Corp.

19-5373; Rev 2; 2/12

Summary of content (132 pages)

PAGE 1
9-5373; Rev 2; 2/12 71M6533/G/H and 71M6534/H Energy Meter ICs DATA SHEET GENERAL DESCRIPTION FEATURES The Teridian™ 71M6533 and 71M6534 are third-generation polyphase metering systems-on-chips (SoCs) with a 10MHz 8051compatible MPU core, low-power RTC, flash, and LCD driver.
PAGE 2
71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 Table of Contents 1 2 2 Hardware Description .................................................................................................................... 9 1.1 Hardware Overview ............................................................................................................... 9 1.2 Analog Front End (AFE)........................................................................................................ 9 1.2.
PAGE 3
FDS_6533_6534_004 3 4 71M6533/G/H and 71M6534/H Data Sheet 2.3.2 LCD Mode ................................................................................................................. 59 2.3.3 SLEEP Mode............................................................................................................. 59 2.4 Fault and Reset Behavior ................................................................................................... 65 2.4.1 Reset Mode .......................................
PAGE 4
71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 5 Electrical Specifications ............................................................................................................ 107 5.1 Absolute Maximum Ratings.............................................................................................. 107 5.2 Recommended External Components ............................................................................. 108 5.3 Recommended Operating Conditions................................
PAGE 5
FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet Figures Figure 2: General Topology of a Chopped Amplifier ............................................................................... 12 Figure 4: AFE Block Diagram................................................................................................................. 14 Figure 5: Samples from Multiplexer Cycle .............................................................................................. 17 Figure 7: Interrupt Structure .
PAGE 6
71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 Tables Table 1: Signals Selected for the ADC with SLOTn_SEL and SLOTn_ALTSEL (MUX_DIV[3:0] = 7) ........... 11 Table 2: ADC Resolution ....................................................................................................................... 11 Table 3: ADC RAM Locations ................................................................................................................ 12 Table 4: XRAM Locations for ADC Results ..............
PAGE 7
FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet Table 68: Recommended External Components .................................................................................. 108 Table 69: Recommended Operating Conditions ................................................................................... 108 Table 70: Input Logic Levels ................................................................................................................ 109 Table 71: Output Logic Levels ...................
PAGE 8
71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 VREF V3P3A V3P3SYS ∆Σ ADC CONVERTER VBIAS FIR VADC MUX 22 VREF VREF VBAT PLS_INV PLS_INTERVAL PLS_MAXWIDTH CE_LCTN EQU PRE_SAMPS SUM_CYCLES RTM_0...3 RTM_E CE_E CE_PROG 16 TEMP 2.
PAGE 9
FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet 1 Hardware Description 1.1 Hardware Overview The Teridian 71M6533 and 71M6534 single-chip energy meter integrate all primary functional blocks required to implement a solid-state electricity meter.
PAGE 10
71M6533/G/H and 71M6534/H Data Sheet 1.2.2 FDS_6533_6534_004 Input Multiplexer The input multiplexer applies the input signals from the pins IAP/IAN, VA, IBP/IBN, VB, ICP/ICN, VC, and IDP/IDN to the input of the ADC. Additionally, using the alternate multiplexer selection, it has the ability to select temperature and the battery voltage. One input is applied per time slot. The multiplexer can implement from one to 10 time slots (states) per frame as controlled by the I/O RAM field MUX_DIV[3:0].
PAGE 11
FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet Table 1: Signals Selected for the ADC with SLOTn_SEL and SLOTn_ALTSEL (MUX_DIV[3:0] = 7) Regular Slot Time Slot 0 1 2 3 4 5 6 Alternate Slot Typical Selections Register SLOT0_SEL[3:0] SLOT1_SEL[3:0] SLOT2_SEL[3:0] SLOT3_SEL[3:0] SLOT4_SEL[3:0] SLOT5_SEL[3:0] SLOT6_SEL[3:0] SLOT7_SEL[3:0] SLOT8_SEL[3:0] SLOT9_SEL[3:0] Signal Number 0 1 2 3 4 5 6 – – – Signal for ADC IA VA IB VB IC VC ID – – – Register SLOT0_ALTSEL[3:0] SLOT1_ALTSEL[3:0] SLOT2_ALT
PAGE 12
71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 Table 3: ADC RAM Locations Signal Number Address (HEX) Name Signal Number 0 1 2 3 4 0x00 0x01 0x02 0x03 0x04 IA VA IB VB IC 5 6 0x0A 0x0B 1.2.5 Address (HEX) 0x05 0x06 0x0A 0x0B Name VC ID TEMP VBAT Voltage References The device includes an on-chip precision bandgap voltage reference that incorporates auto-zero techniques. The reference is trimmed in production to minimize errors caused by component mismatch and drift.
PAGE 13
FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet CHOP_E[1:0] has four states: positive, reverse, and two toggle states. In the positive state, CHOP_E[1:0] = 01, CROSS and CHOP_CLK are held low. In the reverse state, CHOP_E[1:0] = 10, CROSS and CHOP_CLK are held high. In the first toggle state, CHOP_E [1:0] = 00, CROSS is automatically toggled near the end of each multiplexer frame and an ALT frame is forced during the last multiplexer frame in each SUM cycle.
PAGE 14
71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 VREF IAP IAN VA IBP IBN VB ICP ICN VC IDP IDN ∆Σ ADC CONVERTER VBIAS MUX FIR VADC VREF EQU MUX_ALT MUX_DIV VBIAS VREF_CAL VREF_DIS FIR_LEN 22 VB_REF ADC_E VREF VBAT TEMP Figure 4: AFE Block Diagram 1.3 Digital Computation Engine (CE) The CE, a dedicated 32-bit signal processor, performs the precision computations necessary to accurately measure energy.
PAGE 15
FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet Table 4: XRAM Locations for ADC Results Address (HEX) Name Description 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 – 0x09 0x0A 0x0B IA VA IB VB IC VC ID – TEMP VBAT Phase A current Phase A voltage Phase B current Phase B voltage Phase C current Phase C voltage Neutral current Not used Temperature Battery Voltage The CE is aided by support hardware to facilitate implementation of equations, pulse counters, and accumulators.
PAGE 16
71M6533/G/H and 71M6534/H Data Sheet 1.3.2 FDS_6533_6534_004 Real-Time Monitor The CE contains a Real-Time Monitor (RTM), which can be programmed to monitor four selectable XRAM locations at full sample rate. The four monitored locations are serially output to the TMUXOUT pin via the digital output multiplexer at the beginning of each CE code pass. The RTM can be enabled and disabled with the RTM_E bit.
PAGE 17
FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet The Data RAM is 32 bits wide and uses an external multiplexer so as to appear byte-wide to the MPU. The Data RAM hardware will convert an MPU byte write operation into a read-modify-write operation that requires two Data RAM accesses. The second access is guaranteed to be available because the MPU cannot access the XRAM on two consecutive instructions unless it is using the same address.
PAGE 18
71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 833ms 20ms XFER_BUSY Interrupt to MPU Figure 6: Accumulation Interval Figure 6 shows the accumulation interval resulting from PRE_SAMPS[1:0] = 42 and SUM_CYCLES[5:0] = 50, consisting of 2100 samples of 397µs each, followed by the XFER_BUSY interrupt. The sampling in this example is applied to a 50 Hz signal.
PAGE 19
FDS_6533_6534_004 1.4 71M6533/G/H and 71M6534/H Data Sheet 80515 MPU Core The 71M6533 and 71M6534 include an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one clock cycle. Using a 10 MHz clock results in a processing throughput of 10 MIPS. The 80515 architecture eliminates redundant bus states and implements parallel execution of fetch and execution phases.
PAGE 20
71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 If the MPU overwrites the CE’s working RAM, the CE’s output may be corrupted. If the CE is disabled, the first 0x40 bytes of RAM are still unusable while MUX_DIV[3:0] ≠ 0 because the 71M6533/71M6534 ADC writes to these locations. Setting MUX_DIV[3:0] = 0 disables the ADC output, preventing the CE from writing the first 0x40 bytes of RAM. The 80515 writes into external data memory when the MPU executes a MOVX @Ri,A or MOVX @DPTR,A instruction.
PAGE 21
FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet The user switches between pointers by toggling the LSB of the DPS register. The values in the data pointers are not affected by the LSB of the DPS register. All DPTR related instructions use the currently selected DPTR for any activity. The second data pointer may not be supported by certain compilers.
PAGE 22
71M6533/G/H and 71M6534/H Data Sheet Bit Hex/ Addressable Bin X000 X001 D8 WDCON D0 PSW C8 T2CON C0 IRCON B8 IEN1 IP1 B0 P3 A8 IEN0 IP0 A0 P2 DIR2 98 S0CON S0BUF 90 P1 DIR1 88 TCON TMOD 80 P0 SP 1.4.
PAGE 23
FDS_6533_6534_004 Name IEN0 IP0 S0RELL P3 IEN1 IP1 S0RELH S1RELH PDATA IRCON T2CON PSW WDCON A B Address (Hex) 0xA8 0xA9 0xAA 0xB0 0xB8 0xB9 0xBA 0xBB 0xBF 0xC0 0xC8 0xD0 0xD8 0xE0 0xF0 71M6533/G/H and 71M6534/H Data Sheet Reset value Description (Hex) 0x00 0x00 0xD9 0xFF 0x00 0x00 0x03 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Page Interrupt Enable Register 0 Interrupt Priority Register 0 Serial Port 0, Reload Register, low byte Port 3 Interrupt Enable Register 1 Interrupt Priority Register 1 Serial Port
PAGE 24
71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 Stack Pointer (SP, SFR 0x81): The stack pointer is a 1-byte register initialized to 0x07 after reset. This register is incremented before PUSH and CALL instructions, causing the stack to begin at location 0x08. Data Pointer: The data pointers (DPTR and DPRT1) are 2 bytes wide. The lower part is DPL(SFR 0x82) and DPL1 (SFR 0x84) and the highest is DPH (SFR 0x83) and DPH1 (SFR 0x85). The data pointers can be loaded as two registers (e.g.
PAGE 25
FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet Table 13: Stretch Memory Cycle Width 1.4.4 CKCON[2:0] Stretch Value 000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7 Read Signal Width memaddr memrd 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 Write Signal Width memaddr memwr 2 1 3 1 4 2 5 3 6 4 7 5 8 6 9 7 71M6533/71M6534-Specific Special Function Registers Table 14 shows the location and description of the 71M6533/71M6534-specific SFRs.
PAGE 26
71M6533/G/H and 71M6534/H Data Sheet Register (Alternate Name) IFLAGS SFR Address Bit Field Name R/W 0xE8[0] IE_XFER R/W 0xE8[1] IE_RTC R/W 0xE8[2] FW_COL1 R/W 0xE8[3] FW_COL0 R/W 0xE8[4] IE_PB R/W 0xE8[5] IE_WAKE R/W 0xE8[6] PLL_RISE R/W 0xE8[7] PLL_FALL R/W 0xF8[6:0] INT6 … INT0 INTBITS (INT0 … INT6) FDS_6533_6534_004 0xF8[7] WD_RST R W Description This flag monitors the XFER_BUSY interrupt. It is set by hardware and must be cleared by the interrupt handler.
PAGE 27
FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet WDCON[7] selects whether timer 1 or the internal baud rate generator is used. All UART transfers are programmable for parity enable, parity, 2 stop bits/1 stop bit and XON/XOFF options for variable communication baud rates from 300 to 38400 bps. Table 15 shows how the baud rates are calculated. Table 16 shows the selectable UART operation modes.
PAGE 28
71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 Table 17: The S0CON (UART0) Register (SFR 0x98) Bit Symbol S0CON[7] SM0 S0CON[6] SM1 S0CON[5] S0CON[4] SM20 REN0 S0CON[3] TB80 S0CON[2] RB80 S0CON[1] TI0 S0CON[0] RI0 Function The SM0 and SM1 bits set the UART0 mode: Mode Description SM0 SM1 0 N/A 0 0 1 8-bit UART 0 1 2 9-bit UART 1 0 3 9-bit UART 1 1 Enables the inter-processor communication feature. If set, enables serial reception. Cleared by software to disable reception.
PAGE 29
FDS_6533_6534_004 1.4.7 71M6533/G/H and 71M6534/H Data Sheet Timers and Counters The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be configured for counter or timer operations. In timer mode, the register is incremented every 12 MPU clock cycles. In counter mode, the register is incremented when the falling edge is observed at the corresponding input signal T0 or T1 (T0 and T1 are the timer gating inputs derived from certain DIO pins, see Section 1.5.
PAGE 30
71M6533/G/H and 71M6534/H Data Sheet timer. Selects the mode for Timer/Counter 1 as shown in Table 20. TMOD[5:4] M1:M0 Timer/Counter 0 TMOD[3] Gate TMOD[2] C/T TMOD[1:0] M1:M0 FDS_6533_6534_004 If TMOD[3] is set, external input signal control is enabled for Counter 0. external gate control. The TR0 bit in the TCON register (SFR 0x88) must also be set in order for Counter 0 to increment.
PAGE 31
FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet is terminated by a return from instruction, RETI. When an RETI is performed, the processor will return to the instruction that would have been next when the interrupt occurred. When the interrupt condition occurs, the processor will also indicate this by setting a flag bit. This bit is set regardless of whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per machine cycle, then samples are polled by the hardware.
PAGE 32
71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 Table 27: TCON Bit Functions (SFR 0x88) Bit TCON[7] TCON[6] TCON[5] TCON[4] TCON[3] Symbol TF1 TR1 TF0 TR0 IE1 TCON[2] IT1 TCON[1] IE0 TCON[0] IT0 Function Timer 1 overflow flag. Not used for interrupt control. Timer 0 overflow flag. Not used for interrupt control. External interrupt 1 flag. External interrupt 1 type control bit: 0 = interrupt on low level. 1 = interrupt on falling edge.
PAGE 33
FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet External MPU Interrupts The seven external interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of the 71M6533/71M6534, for example the CE, DIO, RTC, EEPROM interface. The external interrupts are connected as shown in Table 30. The polarity of interrupts 2 and 3 is programmable in the MPU via the I3FR and I2FR bits in T2CON.
PAGE 34
71M6533/G/H and 71M6534/H Data Sheet Interrupt Enable Name Location EX_XFER 2002[0] EX_RTC 2002[1] IEN_WD_NROVF 20B0[0] IEN_SPI 20B0[4] EX_FWCOL 2007[4] EX_PLL 2007[5] FDS_6533_6534_004 Interrupt Flag Name Location IE_XFER SFR E8[0] IE_RTC SFR E8[1] WD_NROVF_FLAG 20B1[0] SPI_FLAG 20B1[4] IE_FWCOL0 SFR E8[3] IE_FWCOL1 SFR E8[2] IE_PLLRISE SFRE8[6] IE_PLLFALL SFRE8[7] IE_WAKE SFRE8[5] IE_PB SFRE8[4] Interrupt Description XFER_BUSY interrupt (INT 6) RTC_1SEC interrupt (INT 6) WDT near overflow (INT 6) SP
PAGE 35
FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet Table 34: Interrupt Priority Registers (IP0 and IP1) Register Address Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 IP0 IP1 SFR 0xA9 SFR 0xB9 – – – – IP0[5] IP1[5] IP0[4] IP1[4] IP0[3] IP1[3] IP0[2] IP1[2] IP0[1] IP1[1] Bit 0 (LSB) IP0[0] IP1[0] External interrupt 0 Serial channel 1 interrupt Timer 0 interrupt External interrupt 2 External interrupt 1 External interrupt 3 Timer 1 interrupt External interrupt 4 Serial channel 0 int
PAGE 36
71M6533/H and 71M6534/H Data Sheet FDS_6533_6534_004 No. External Source Internal Source Individual Enable Bits Individual Flags 0 DIO DIO status changed DIO_Rn TCON.1 (IE0) byte received S1CON.0 (RI1) byte transmitted S1CON.1 (TI1) Timer 0 SPI I/F 2 Write attempt, CE Flash busy Write CE code start, Collision TCON.
PAGE 37
FDS_6533_6534_004 1.5 71M6533/G/H and 71M6534/H Data Sheet On-Chip Resources 1.5.1 Oscillator The 71M6533/71M6534 oscillator drives a standard 32.768 kHz watch crystal. These crystals are accurate and do not require a high-current oscillator circuit. The oscillator has been designed specifically to handle these crystals and is compatible with their high impedance and limited power handling capability.
PAGE 38
71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 The PLL has a 2x emulator clock which is controlled by the ECK_DIS bit. Since clock noise from this feature may disturb the ADC, it is recommended that this option be avoided when possible. The MPU clock frequency CKMPU is determined by another divider controlled by the I/O RAM field (MPU_DIV+2) Hz where MPU_DIV[2:0] varies from 0 to 6. The circuit MPU_DIV[2:0] and can be set to MCK/2 also generates the 2 x CKMPU clock for use by the emulator.
PAGE 39
FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet The second rate adjustment is a digital rate adjust using PREG[16:0] and QREG[1:0], which can be used to adjust the clock rate up to ± 988 ppm, with a resolution of 3.8 ppm. Updates must occur after a one second interrupt, and must finish before the next one second boundary. The rate adjustment will be implemented starting at the next one-second boundary.
PAGE 40
71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 The flash memory is segmented into individually erasable pages that contain 1024 bytes. Flash space allocated for the CE program is limited to 4096 16-bit words (8 KB). The CE program must begin on a 1 KB boundary of the flash address space. The CE_LCTN[7:0] word defines which 1 KB boundary contains the CE code. Thus, the first CE instruction is located at 1024*CE_LCTN[7:0]. Flash Write Procedures The MPU may write to the flash memory.
PAGE 41
FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet The page erase sequence is: 1. Write the page address to FLSH_PGADR[5:0] (SFR 0xB7[7:2]). 2. Write the pattern 0x55 to FLSH_ERASE (SFR 0x94). Note: Transitions to BROWNOUT mode must be avoided during page erase operations. Bank-Switching The program memory of the 71M6533/71M6534 consists of a fixed lower bank of 32 KB, addressable at 0x0000 to 0x7FFF plus an upper banked area of 32 KB, addressable at 0x8000 to 0xFFFF.
PAGE 42
71M6533/G/H and 71M6534/H Data Sheet 1.5.6 FDS_6533_6534_004 Optical Interface The device includes an interface to implement an IR/optical port. The pin OPT_TX is designed to directly drive an external LED for transmitting data on an optical link. The pin OPT_RX has the same threshold as the RX pin, but can also be used to sense the input from an external photo detector used as the receiver for the optical link. OPT_TX and OPT_RX are connected to a dedicated UART port (UART1).
PAGE 43
FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet On reset or power-up, all DIO pins are inputs until they are configured for the desired direction under MPU control. The pin function can be configured by the I/O RAM bits LCD_BITMAPn. Setting LCD_BITMAPn = 1 configures the pin for LCD, setting LCD_BITMAPn = 0 configures it for DIO. Once a pin is configured as DIO, it can be configured independently as an input or output with the DIO_DIR bits or the LCD_SEGn registers.
PAGE 44
71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 Table 41: Data/Direction Registers and Internal Resources for DIO 36-47 LCD_SEG67[0] LCD_SEG59[3]* LCD_SEG67[3] LCD_SEG58[3]* LCD_SEG66[0]* LCD_SEG57[3]* LCD_SEG66[3]* – LCD_SEG65[0] – LCD_SEG65[3] LCD_SEG59[0]* – LCD_SEG64[0] LCD_SEG58[0]* – LCD_SEG64[3] LCD_SEG57[0]* Direction Register 0 = input, 1 = output – LCD_SEG63[0] – LCD_SEG63[3] – 44 45 46* 47 64 65 66* 67 31 38 – 22 37 44 5 27 0 1 2* 3 LCD_BITMAP[71:64] LCD_SEG62[0
PAGE 45
FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet Since the control for DIO_24 through DIO_55 is shared with the control for LCD segments, the firmware must take care not to disturb the DIO pins when accessing the LCD segments and vice versa. Usually, this requires reading the I/O RAM register, applying a mask and writing back the modified byte. DIO4 and DIO5 can be configured to implement the EEPROM Interface.
PAGE 46
71M6533/G/H and 71M6534/H Data Sheet MISSION LCD/SLEEP BROWNOUT FDS_6533_6534_004 V3P3SYS MISSION VBAT BROWNOUT LCD/SLEEP V3P3D HIGH HIGH-Z DIO LOW VBAT V3P3D HIGH HIGH-Z LOW GNDD Not recommended V3P3SYS DIO GNDD Recommended Figure 9: Connecting an External Load to DIO Pins 1.5.
PAGE 47
FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet modes, VBAT in LCD mode). When the LCD_DAC[2:0] bits are set to 000, the DAC is bypassed and powered down. This can be used to reduce current in LCD mode. 1.5.9 Battery Monitor The battery voltage is measured by the ADC during alternative MUX frames if the BME (Battery Measure Enable) bit is set. While BME is set, an on-chip 45 kΩ load resistor is applied to the battery and a scaled fraction of the battery voltage is applied to the ADC input.
PAGE 48
71M6533/G/H and 71M6534/H Data Sheet Status Bit Name Read/ Write Reset State Polarity FDS_6533_6534_004 Description 0110 1001 Others Receive the last byte from the EEPROM and do not send ACK. Issue a START sequence. No operation, set the ERROR bit. The EEPROM interface can also be operated by controlling the DIO4 and DIO5 pins directly.
PAGE 49
FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet EECTRL Byte Written INT5 CNT Cycles (6 shown) Write -- No HiZ SCLK (output) SDATA (output) D7 D6 D5 SDATA output Z D4 D3 D2 (LoZ) BUSY (bit) Figure 10: 3-wire Interface. Write Command, HiZ=0. EECTRL Byte Written INT5 CNT Cycles (6 shown) Write -- With HiZ SCLK (output) SDATA (output) D7 D6 D5 SDATA output Z D4 D3 D2 (LoZ) (HiZ) BUSY (bit) Figure 11: 3-wire Interface.
PAGE 50
71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 1.5.11 SPI Slave Port The slave SPI port communicates directly with the MPU data bus and is able to read and write Data RAM locations. It is also able to send commands to the MPU. The interface to the slave port consists of the PCSZ, PCLK, PSDI and PSDO pins. These pins are multiplexed with the LCD segment driver pins SEG3 to SEG6. The port pins default to LCD driver pins. The port is enabled by setting the SPE bit.
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FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet The SPI_FLAG flag bit will be set upon every SPI transaction regardless of whether the command is 11xx xxxx or 10xx xxxx. The SP_ADDR[15:0] bit field is for writing purposes by the host only. Data read from SP_ADDR[15:0] will not contain the next available SPI address after an auto-increment operation. The last issued SPI command and address (if part of the command) are available to the MPU in registers SP_CMD and SP_ADDR.
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71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 command so the MPU can access the bus. There are no issues with Data RAM access; SPI and the MPU will share the bus with no conflicts for Data RAM access.
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FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet SERIAL READ 8 bit CMD DATA[ADDR] 16 bit Address DATA[ADDR+1] Extended Read . . . PCSZ 0 7 8 C0 A15 23 24 A0 x 31 32 D0 D7 39 PSCK (From Host) PSDI x C7 C6 C5 A14 A1 HI Z (From 653X) PSDO SERIAL WRITE D7 8 bit CMD D6 D1 DATA[ADDR] 16 bit Address D1 D0 DATA[ADDR+1] PCSZ Extended Write . . .
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71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 If enabled with the IEN_WD_NROVF bit in I/O RAM, an interrupt occurs roughly 1 ms before the WDT resets the chip. This can be used to determine the cause of a WDT reset since it allows the code to log its state (e.g. the current PC value, loop counters, flags, etc.) before a WDT reset occurs. 1.5.13 Test Ports (TMUXOUT Pin) One of the digital or analog signals listed in Table 49 can be selected to be output on the TMUXOUT pin.
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FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet 2 Functional Description 2.
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71M6533/G/H and 71M6534/H Data Sheet 2.2 FDS_6533_6534_004 System Timing Summary Figure 19 summarizes the timing relationships between the input MUX states, the CE_BUSY signal and the two serial output streams. In this example, MUX_DIV[3:0] = 6 and FIR_LEN[1:0] = 1.
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FDS_6533_6534_004 2.3 71M6533/G/H and 71M6534/H Data Sheet Battery Modes Shortly after system power (V3P3SYS) is applied, the part will be in MISSION mode. MISSION mode means that the part is operating with system power and that the internal PLL is stable. This mode is the normal operation mode where the part is capable of measuring energy. When system power is not available (i.e. when V1
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71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 To facilitate transition to SLEEP mode, which is useful when an unprogrammed IC is mounted on a PCB with a battery installed, the Teridian production test programs the following six-byte sequence into the flash location starting at address 0x00000: 0x74 - 0x40 - 0x90 - 0x20 - 0xA9 - 0xF0.
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FDS_6533_6534_004 2.3.1 71M6533/G/H and 71M6534/H Data Sheet BROWNOUT Mode In BROWNOUT mode, most non-metering digital functions are active (as shown in Table 50) including ICE, UART, EEPROM, LCD and RTC. In BROWNOUT mode, a low-bias current regulator will provide 2.5 Volts to V2P5 and V2P5NV. The regulator has an output called BAT_OK to indicate that it has sufficient overhead. When BAT_OK = 0, the part will enter SLEEP mode. From BROWNOUT mode, the processor can voluntarily enter LCD or SLEEP modes.
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71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 System (V3P3SYS) V1_OK Battery Current MPU Mode 300 nA BROWNOUT PLL_OK MISSION 13..14 CK cycles WAKE MPU Clock Source Transition PLL (4.2 MHz/MUX_DIV) Xtal 2048...4096 CK32 cycles Power Figure 22: Transition from BROWNOUT to MISSION Mode when System Power Returns V3P3SYS and VBAT V1_OK Battery Current MPU Mode MPU Clock Source WAKE PLL_OK Internal RESETZ 300 nA BROWNOUT Xtal MISSION PLL (4.2 MHz) 14.
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FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet VBAT Battery Current BROWNOUT MPU Mode MPU Clock Source WAKE Xtal 14.
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71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 GNDA GNDD VREF ∆Σ ADC CONVERTER VBIAS FIR VADC MUX 22 VREF VREF VBAT PLS_INV PLS_INTERVAL PLS_MAXWIDTH CE_LCTN EQU PRE_SAMPS SUM_CYCLES RTM_0...3 RTM_E CE_E CE_PROG 16 TEMP 2.
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FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet GNDA GNDD VREF ∆Σ ADC CONVERTER VBIAS FIR VADC MUX 22 VREF VREF VBAT PLS_INV PLS_INTERVAL PLS_MAXWIDTH CE_LCTN EQU PRE_SAMPS SUM_CYCLES RTM_0...3 RTM_E CE_E CE_PROG 16 TEMP 2.
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71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 VREF IAP IAN VA IBP IBN VB ICP ICN VC IDP IDN GNDA GNDD V3P3A V 3P 3SYS ∆Σ ADC CONVERTER VBIAS RTM PLS_INV FIR PLS_INTERVAL to TMUX 22 PLS_MAXWIDTH CE_LCTN VOLT RPULSE EQU REG PRE_SAMPS WPULSE LCD_ONLY SUM_CYCLES VREF SLEEP RTM_0...3 XPULSE RTM_E YPULSE CE_E E EEE S SSS CE_DATA CE_PROG L L L L U UUU 2. 5V to logic 16 32 PP P PW Y X R 2 .5V _NV VADC MUX VREF VBAT TEMP 2 .
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FDS_6533_6534_004 2.4 2.4.1 71M6533/G/H and 71M6534/H Data Sheet Fault and Reset Behavior Reset Mode When the RESET pin is pulled high, all digital activity stops. The oscillator and RTC module continue to run. Additionally, all I/O RAM bits are set to their default states. As long as V1, the input voltage at the power fault block, is greater than VBIAS, the internal 2.5 V regulator will continue to provide power to the digital section.
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71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 System Power (V3P3SYS) PB or wakeup timer 15 CK32 cycles WAKE MPU Mode LCD BROWNOUT PLL_OK time Figure 28: Wake Up Timing 2.5.2 Wake on Timer If the part is in SLEEP or LCD mode, it can be awakened by the wake-up timer. Until this timer times out, the MPU is in reset due to WAKE being low. When the wake-up timer times out, the WAKE signal rises and within three CK32 cycles, the MPU begins to execute.
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FDS_6533_6534_004 2.7 71M6533/G/H and 71M6534/H Data Sheet CE/MPU Communication Figure 30 shows the functional relationships between the CE and the MPU. The CE is controlled by the MPU via shared registers in the I/O RAM and in RAM. The CE outputs two interrupt signals to the MPU: CE_BUSY and XFER_BUSY, which are connected to the MPU interrupt service inputs as external interrupts. CE_BUSY indicates that the CE is actively processing data. This signal will occur once every multiplexer cycle.
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71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 3 Application Information 3.1 Connection of Sensors (CT, Resistive Shunt) Figure 31 through Figure 33 show how resistive dividers, current transformers, Rogowski coils and resistive shunts are connected to the voltage and current inputs of the 71M6533/71M6534. The analog input pins of the 71M65XX are designed for sensors with low source impedance.
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FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet correction coefficients PPM1 and PPMC2 per the formulae given in Section 6.4.15 VREF. See Section 3.5 Temperature Compensation for additional details. The fuse TRIMBGB is non-zero for the high-accuracy parts and zero for the regular parts. Only partial trim fuse information is available for the regular parts. The values for PPMC and PPMC2 that are used by the CE to implement temperature compensation are calculated as follows: • • PPMC = TC1 * 22.
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71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 Since TC1 and TC2 are given in µV/°C and µV/°C2, respectively, the value of the VREF voltage (1.195V) has to be taken into account when transitioning to PPM/°C and PPM/°C2. This means that PPMC = 26.84*TC1/1.195 and PPMC2 = 1374*TC2/1.195).
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FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet Error Band (PPM) over Temperature (°C) 2800 2400 2000 1600 1200 800 400 0 -400 -800 -1200 -1600 -2000 -2400 -2800 ±40 PPM/°C ±40 PPM/°C -40 -20 0 20 40 60 80 Figure 34: Error Band for VREF over Temperature (Regular-Accuracy Parts) Error Band (PPM) over Temperature (°C) 1200 ±15 PPM/°C 800 400 0 -400 -800 ±15 PPM/°C -1200 -40 -20 0 20 40 60 80 Figure 35: Error Band for VREF over Temperature (High-Accuracy Parts) 4.1.
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71M6533/G/H and 71M6534/H Data Sheet 4.1.2 FDS_6533_6534_004 System Temperature Compensation In a production electricity meter, the 71M6533 and 71M6534 is not the only component contributing to temperature dependency. A whole range of components (e.g. current transformers, resistor dividers, power sources, filter capacitors) will contribute temperature effects.
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FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet 71M6533/71M6534 LCD segments commons Figure 36: Connecting LCDs Connecting I2C EEPROMs 4.3 I2C EEPROMs or other I2C compatible devices should be connected to the DIO pins DIO4 and DIO5, as shown in Figure 37. Pull-up resistors of roughly 10 kΩ to V3P3D (to ensure operation in BROWNOUT mode) should be used for both SCL and SDA signals.
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71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 71M6533/71M6534 EEPROM V3P3D VCC DIO4 CLK DI 10 kΩ DIO5 DIOn DO CS 100 kΩ 100 kΩ Figure 38: Three-Wire EEPROM Connection 4.5 UART0 (TX/RX) The UART0 RX pin should be pulled down by a 10 kΩ resistor and additionally protected by a 100 pF ceramic capacitor, as shown in Figure 39. 71M6533/71M6534 RX TX 100 pF 10 k Ω RX TX Figure 39: Connections for UART0 4.
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FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet V3P3SYS R1 71M6533/71M6534 100 pF OPT_RX 10 kΩ Phototransistor V3P3SYS LED R2 OPT_TX Figure 40: Connection for Optical Components 4.7 Connecting the V1 Pin A voltage divider should be used to establish that V1 is in a safe range when the meter is in MISSION mode (see Figure 41). V1 must be lower than 2.9 V in all cases in order to keep the hardware watchdog timer enabled.
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71M6533/G/H and 71M6534/H Data Sheet VBAT/ V3P3D FDS_6533_6534_004 71M6533/ 71M6534 71M6533/ 71M6534 V3P3D R2 1k ? Reset Switch RESET 10k ? R1 0.1µF GNDD Figure 42: External Components for the RESET Pin: Push-Button (Left), Production Circuit (Right) 4.9 Connecting the Emulator Port Pins Even when the emulator is not used, small shunt capacitors to ground (22 pF) should be used for protection from EMI as illustrated in Figure 43.
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FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet Power Supply V3P3SYS V3P3A DIO Battery or + Super -Cap - VBAT 71M6533/6534 Figure 44: Connecting a Battery Meters equipped with batteries need to contain code that transitions the chip to SLEEP mode as soon as the battery is attached in production. Otherwise, remaining in BROWNOUT mode would add unnecessary drain to the battery. 4.
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71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 4.14 Meter Calibration Once the Teridian 71M6533 and 71M6534 energy meter device has been installed in a meter system, it must be calibrated. A complete calibration includes the following: • • • • Calibration of the metrology section, i.e. calibration for tolerances of the current sensors, voltage dividers and signal conditioning components as well as of the internal reference voltage (VREF). Establishment of the reference temperature (Section 3.
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FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet 5 Firmware Interface 5.1 I/O RAM and SFR Map –Functional Order In Table 53, unimplemented (U) and reserved (R) bits are shaded in light gray. Unimplemented bits have no memory storage, writing them has no effect, and reading them always returns zero. Reserved bits may be in use and should not be changed from the values given in parentheses.
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71M6533/G/H and 71M6534/H Data Sheet Name Address Digital I/O: 20AF DIO0 2008 DIO1 2009 DIO2 200A DIO3 200B DIO4 200C DIO5 200D DIO6 200E 200F Bit 7 FDS_6533_6534_004 Bit 6 U U DIO_EEX[1:0] U U U U U U R (00) † UMUX_E UMUX_SEL† DIO7/ P0 DIO8 DIO9 / P1 (Port 1) SFR 80 SFR A2 SFR 90 DIO_1[7:5] DIO10 SFR 91 DIO_DIR1[7:5] DIO11/ P2 SFR A0 (Port 2) DIO_2[7] Bit 5 Bit 4 Bit 3 U OPT_RXDIS DIO_R1[2:0] DIO_R3[2:0] DIO_R5[2:0] DIO_R7[2:0] DIO_R9[2:0] DIO_R11[2:0] U OPT_RXINV U DIO_PW U U U U U U U
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FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet Name Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RTC0 RTC_SEC[5:0] 2015 U U RTC1 RTC_MIN[5:0] 2016 U U RTC2 RTC_HR[4:0] 2017 U U U RTC3 RTC_DAY[2:0] 2018 U U U U U RTC4 RTC_DATE[2:0] 2019 U U U RTC5 RTC_MO[3:0] 201A U U U U RTC6 RTC_YR[7:0] 201B RTCADJ_H 201C PREG[16:14] U U U U U RTCADJ_M 201D PREG[13:6] RTCADJ_L 201E PREG[5:0] QREG[1:0] WE 201F RTC write protect register (write data is discarded) LCD Display Interface: LCDX MUX_SYNC_E BM
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71M6533/G/H and 71M6534/H Data Sheet Name Address SPI Interface: SPI… 2070 SP_CMD 2071 SP_ADH 2072 SP_ADL 2073 Pulse Generator: PLS_W 2080 PLS_I 2081 ADC Mux: SLOT0 2090 SLOT1 2091 SLOT2 2092 SLOT3 2093 SLOT4 2094 SLOT5 2096 SLOT6 2097 SLOT7 2098 SLOT8 2099 SLOT9 209A SPI Interrupt: FDS_6533_6534_004 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SPE U U U U U U U SP_CMD[7:0] SP_ADDR[15:8] SP_ADDR[7:0] PLS_MAXWIDTH[7:0] PLS_INTERVAL[7:0] SLOT1_SEL[3:0] SLOT3_SEL[3:0] SLOT5_SEL[3:0] SLOT7_
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FDS_6533_6534_004 5.2 71M6533/G/H and 71M6534/H Data Sheet I/O RAM Description – Alphabetical Order The following conventions apply to the descriptions in this table: • • • • • Bits with a W (write) direction are written by the MPU into configuration RAM. Typically, they are initially stored in flash memory and copied to the configuration RAM by the MPU. Some of the more frequently programmed bits are mapped to the MPU SFR memory space. The remaining bits are mapped to 2xxx.
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71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 CKOUT_E 2004[4] 0 0 R/W COMPSTAT 2003[0] -- -- R DI_RPB[2:0] DIO_R1[2:0] DIO_R2[2:0] DIO_R3[6:4] DIO_R4[2:0] DIO_R5[2:0] DIO_R6[2:0] DIO_R7[2:0] DIO_R8[2:0] DIO_R9[2:0] DIO_R10[2:0] DIO_R11[2:0] DIO_RRX[2:0]* 2009[2:0] 2009[6:4] 200A[2:0] 200A[6:4] 200B[2:0] 200B[6:4] 200C[2:0] 200C[6:4] 200D[2:0] 200D[6:4] 200E[2:0] 200E[6:4] 20AF[2:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W Control bit for the SEG19/CKOUT pin: 0: The p
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FDS_6533_6534_004 DIO_0[7:0] DIO_1[7:0] DIO_2[7:0] DIO_3[6:0] SFR 80 SFR 90 SFR A0 SFR B0 71M6533/G/H and 71M6534/H Data Sheet 0 0 0 0 – – – – R/W DIO_EEX[1:0] 2008[7:6] 0 0 R/W DIO_PV DIO_PW DIO_PX DIO_PY EEDATA[7:0] EECTRL[7:0] 2008[2] 2008[3] 200F[3] 200F[2] SFR 9E SFR 9F 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W ECK_DIS 2005[5] 0 0 R/W EQU[2:0] EX_XFR EX_RTC EX_FWCOL EX_PLL 2000[7:5] 2002[0] 2002[1] 2007[4] 2007[5] 0 0 0 0 0 0 0 0 0 0 R/W Rev 2 R/W The value on the DIO
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71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 FIR_LEN[1:0] 2007[3:2] 1 1 R/W FL_BANK[1:0] FL_BANK[2:0]† SFR B6[1:0] SFR B6[2:0] 1 1 R/W FLSH_ERASE [7:0] SFR 94[7:0] 0 0 W FLSH_MEEN SFR B2[1] 0 0 W FLSH_PGADR [5:0] SFR B7 [7:2] 0 0 W FLSH_PWE SFR B2[0] 0 0 R/W FOVRIDE 20FD[4] 0 0 R/W 86 FIR_LEN[1:0] controls the length of the ADC decimation FIR filter. Resulting FIR Resulting [M40MHZ, M26MHZ] FIR_LEN[1:0] Filter Cycles ADC Gain [00], [10], or [11] 00 138 0.
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FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet GP0 … GP7 IE_FWCOL0 IE_FWCOL1 20C0 … 20C7 SFR E8[2] SFR E8[3] 0 … 0 0 0 NV … NV 0 0 IE_PB SFR E8[4] 0 – R/W IE_PLLRISE SFR E8[6] 0 0 R/W IE_PLLFALL SFR E8[7] 0 0 R/W IEN_SPI IEN_WD_NROVF IE_XFER IE_RTC 20B0[4] 20B0[0] SFR E8[0] SFR E8[1] 0 0 0 0 0 0 IE_WAKE SFR E8[5] 0 – R/W INTBITS SFR F8[6:0] – – R/W LCD_BITMAP [31:24] 2023[7:0] 0 L R/W LCD_BITMAP [39:32] 2024[7:0] 0 L R/W 2025[7:0] 0 L R/W 2026[2:0] 0
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71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 LCD_BITMAP [63:61], [59:56]† 2027[7:5,3:0] 0 L R/W LCD_BITMAP [71:64] 2028[7:0] 0 L R/W LCD_BLKMAP18 205A[3:0] [3:0] 0 L R/W LCD_CLK[1:0] 0 L R/W 2021[1:0] LCD_DAC[2:0] 20AB[3:1] 0 L R/W LCD_E 2021[5] 0 L R/W LCD_MODE[2:0] 2021[4:2] 88 0 L R/W Configuration for DIO43/SEG63 through DIO41/SEG61 and DIO39/SEG59 through DIO36/SEG56.
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FDS_6533_6534_004 LCD_ONLY 20A9[5] LCD_SEG0[3:0] 2030[3:0] … … LCD_SEG18[3:0] 2042[3:0] LCD_SEG19[3:0] 2043[3:0] … … LCD_SEG31[3:0] 204F[3:0] † LCD_SEG32[3:0] 2050[3:0] LCD_SEG33[3:0] 2051[3:0] … … LCD_SEG41[3:0] 2059[3:0] † LCD_SEG42[3:0] 2030[7:4] LCD_SEG43[3:0] 2031[7:4] … … LCD_SEG47[3:0] 2035[7:4] LCD_SEG48[3:0]† 2036[7:4] LCD_SEG49[3:0] 2037[7:4] LCD_SEG50[3:0] 2038[7:4] LCD_SEG51[3:0]† 2039[7:4] … … LCD_SEG59[3:0]† 2041[7:4] LCD_SEG61[3:0] 2043[7:4] † LCD_SEG62[3:0] 2044[7:4] LCD_SEG63[3:0] 2045[7
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71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 LCD_Y 2021[6] 0 L R/W M26MHZ M40MHZ 2005[4] 2005[0] 0 0 0 0 R/W R/W LCD Blink Frequency (ignored if blink is disabled or if the segment is off). 0 = 1 Hz (500 ms ON, 500 ms OFF) 1 = 0.5 Hz (1 s ON, 1 s OFF) M26MHZ and M40MHZ set the master clock (MCK) frequency. These bits are reset on chip reset and may only be set. Attempts to write zeroes to M40MHZ and M26MHZ are ignored. M40MHZ M26MHZ MCK Frequency 0 0 20 MHz 0 1 26.
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FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet OPT_RXDIS 2008[5] 0 0 R/W OPT_RXINV 2008[4] 0 0 R/W OPT_TXE[1:0] 2007[7:6] 00 00 R/W OPT_TXINV 2008[0] 0 0 R/W OPT_TXMOD 2008[1] 0 0 R/W PLL_OK 2003[6] 0 0 R FF FF R/W PLS_MAXWIDTH 2080[7:0] [7:0] PLS_INTERVAL [7:0] 2081[7:0] 0 0 R/W PLS_INV 2004[6] 0 0 R/W PREBOOT SFRB2[7] – – R PREG[16:0] 201C[2:0] 201D[7:0] 201E[7:2] 4 0 0 NV NV NV R/W R/W R/W PRE_SAMPS[1:0] 2001[7:6] Rev 2 0 0 R/W Configure
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71M6533/G/H and 71M6534/H Data Sheet QREG[1:0] RST_SUBSEC RTCA_ADJ[6:0] 201E[1:0] 2010[0] 2011[6:0] RTC_SEC[5:0 RTC_MIN[5:0] RTC_HR[4:0] RTC_DAY[2:0] RTC_DATE[4:0] RTC_MO[3:0] RTC_YR[7:0] RTM_E RTM0[7:0] RTM1[7:0] RTM2[7:0] RTM3[7:0] FDS_6533_6534_004 0 0 40 NV NV – 2015 2016 2017 2018 2019 201A 201B * * * * * * * NV NV NV NV NV NV NV 2002[3] 2060[9:8] 2061[7:0] 2062[9:8] 2063[7:0] 2064[9:8] 2064[7:0] 2065[9:8] 2066[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W SECURE SFR
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FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet SLOT0_ALTSEL [3:0] SLOT1_ALTSEL [3:0] SLOT2_ALTSEL [3:0] … SLOT8_ALTSEL [3:0] SLOT9_ALTSEL [3:0] SP_ADDR[15:8] SP_ADDR[7:0] SP_CMD SPE 2096[3:0] 10 10 2096[7:4] 1 1 2097[3:0] 11 11 … 209A[3:0] … 8 … 8 209A[7:4] 9 9 2072[7:0] 2073[7:0] 2071 2070[7] – – – 0 – 0 SPI_FLAG 20B1[4] SUBSEC[7:0] 2014[7:0] – – R SUM_CYCLES[5:0] 2001[5:0] 0 0 R/W TMUX[4:0] 20AA[4:0] 2 – R/W TRIM[7:0] 20FF 0 0 R/W TRIMSEL[3:0] 20FD[3:0]
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71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 – – – – VERSION[7:0] 2006 20C8 VREF_CAL VREF_DIS 2004[7] 2004[3] 0 0 0 0 R/W R/W WAKE_ARM 20A9[7] 0 – W WAKE_PRD 20A9[2:0] 001 – R/W WAKE_RES WD_NROVF_ FLAG 20A9[3] 0 – R/W 20B1[0] – 0 R/W WD_RST SFR F8[7] 0 0 W WD_OVF 2002[2] 0 NV* R/W WE WRPROT_BT 201F[7:0] SFR B2[5] 0 0 WRPROT_CE SFR B2[4] 0 0 † R R W The device version index. This word may be read by the firmware to determine the silicon version.
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FDS_6533_6534_004 5.3 71M6533/G/H and 71M6534/H Data Sheet CE Interface Description 5.3.1 CE Program The CE performs the precision computations necessary to accurately measure power. These computations include offset cancellation, phase compensation, product smoothing, product summation, frequency detection, VAR calculation, sag detection and voltage phase measurement. All data computed by the CE is dependent on the selected meter equation as given by EQU[2:0] (in I/O RAM).
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71M6533/G/H and 71M6534/H Data Sheet 5.3.4 FDS_6533_6534_004 Environment Before starting the CE using the CE_E bit, the MPU has to establish the proper environment for the CE by implementing the following steps: • • • • • • • • • Load the CE data into RAM. Establish the equation to be applied in EQU[2:0]. Establish the accumulation period and number of samples in PRE_SAMPS[1:0] and SUM_CYCLES[5:0]. Establish the number of cycles per ADC multiplexer frame (MUX_DIV[3:0]).
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FDS_6533_6534_004 5.3.
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71M6533/G/H and 71M6534/H Data Sheet 5.3.7 FDS_6533_6534_004 CE Status and Control CESTATUS provides information about the status of voltage and input AC signal frequency, which are useful for generating early power fail warnings, e.g. to initiate necessary data storage. It contains sag warning flags for phase A, B, and C, as well as F0, the derived clock operating at the fundamental input frequency. CESTATUS represents the status flags for the preceding CE code pass (CE_BUSY interrupt).
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FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet The EXT_TEMP bit enables temperature compensation mode: • • When EXT_TEMP = 0 (internal compensation), the CE will control the gain using GAIN_ADJ (see Table 59) based on PPMC, PPMC2 and TEMP_X, the difference between die temperature and the reference / calibration temperature TEMP_NOM.
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71M6533/G/H and 71M6534/H Data Sheet [1] PULSE_FAST 0 [0] PULSE_SLOW 0 FDS_6533_6534_004 When PULSE_FAST = 1, the pulse generator input is increased 16x. When PULSE_SLOW = 1, the pulse generator input is reduced by a factor of 64. These two bits control the pulse gain factor X (see table below). Default is 0 for both (X = 6). PULSE_SLOW PULSE_FAST X 0 0 1.5 * 22 = 6 0 1 1.5 * 26 = 96 -4 1 0 1.5 * 2 = 0.
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FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet WSUM_X and VARSUM_X are the signed sum of Phase-A, Phase-B and Phase-C Wh or VARh values according to the metering equation specified in the I/O RAM register EQU[2:0]. WxSUM_X is the Wh value accumulated for phase x in the last accumulation interval and can be computed based on the specified LSB value. For example, with VMAX = 600 V and IMAX = 208 A, the LSB for WxSUM_X is 0.1173 µWh.
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71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 Table 62: Other Transfer Variables CE Address Name 0x82 FREQ_X Description Fundamental frequency: LSB ≡ 0x97 PH_AtoB_X 0x98 PH_AtoC_X 0x83 MAINEDGE_X 0x84 VBAT_SUM_X 5.3.9 FS ≈ 0.587 ⋅ 10 −6 Hz 32 2 Voltage phase lag. The selection of the reference phase is based on FREQSEL1 and FREQSEL0 in the CECONFIG register: If FREQSEL1/FREQSEL0 select phase A: Phase lag from A to B. If FREQSEL1/FREQSEL0 select phase B: Phase lag from B to C.
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FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet The maximum pulse rate is 3*FS = 7.5 kHz. Control is transferred to the MPU for pulse generation if EXT_PULSE = 1. In this case, the pulse rate is determined by APULSEW and APULSER. The MPU loads the source for pulse generation in APULSEW and APULSER to generate pulses. Irrespective of the EXT_PULSE status, the output pulse rate controlled by APULSEW and APULSER is implemented by the CE only.
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71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 5.3.11 Noise Suppression and Version Parameters Table 65 shows the CE parameters used for suppression of noise due to scaling and truncation effects. Table 65: CE Parameters for Noise Suppression and Code Version CE Address 0x26 0x27 0x28 0x2A 0x2B 0x2C Name Default QUANTA QUANTB QUANTC QUANT_VARA QUANT_VARB QUANT_VARC 0 0 0 0 0 0 These parameters are added in channel A to the Watt calculation to compensate for input noise and truncation.
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FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet 5.3.13 CE Flow Diagrams Figure 45 through Figure 47 show the data flow through the CE in simplified form. Functions not shown include delay compensation, sample interpolation, scaling and the processing of meter equations. multiplexer IA VA IB VB IC VC ID VREF ΔΣ mod FS= 2184 Hz Per channel de-multiplexer IA_RAW VA_RAW IB_RAW VB_RAW IC_RAW VC_RAW ID_RAW FIR FCLK= 4.
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71M6533/G/H and 71M6534/H Data Sheet SUM WA WB WC VARA VARB VARC PRE_SAMPS IA IB IC VA VB VC F0 FDS_6533_6534_004 Σ Σ SQUARE I2 V2 IASQ IBSQ ICSQ VASQ VBSQ VCSQ SUM Σ Σ WASUM_X WBSUM_X WCSUM_X VARASUM_X VARBSUM_X VARCSUM_X MPU SUM_CYCLES=60 & PRE_SAMPS = 42 IASQSUM_X IBSQSUM_X ICSQSUM_X VASQSUM_X VBSQSUM_X VCSQSUM_X F0 Figure 47: CE Data Flow: Squaring and Summation Stages 106 Rev 2
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FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet 6 Electrical Specifications 6.1 Absolute Maximum Ratings Table 67 shows the absolute maximum ranges for the device. Stresses beyond Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation at these or any other conditions beyond those indicated under recommended operating conditions (Section 6.3) is not implied.
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71M6533/G/H and 71M6534/H Data Sheet 6.2 FDS_6533_6534_004 Recommended External Components Table 68: Recommended External Components Name C1 C2 CSYS C2P5 From V3P3A V3P3D V3P3SYS V2P5 To AGND GNDD GNDD GNDD XTAL XIN XOUT CXS XIN AGND CXL XOUT AGND Function Bypass capacitor for 3.3 V supply Bypass capacitor for 3.3 V output Bypass capacitor for V3P3SYS Bypass capacitor for V2P5 32.768 kHz crystal – electrically similar to ECS .327-12.5-17X or Vishay XT26T, load capacitance 12.
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FDS_6533_6534_004 6.4 6.4.1 71M6533/G/H and 71M6534/H Data Sheet Performance Specifications Input Logic Levels Table 70: Input Logic Levels Parameter † Digital high-level input voltage , VIH † Digital low-level input voltage , VIL Input pull-up current, IIL E_RXTX, E_ISYNC E_RST, CKTEST Other digital inputs Input pull down current, IIH ICE_E RESET PB Other digital inputs † Condition Min 2 VIN=0 V, ICE_E=1 Typ 10 10 -1 VIN = V3P3D 10 10 -1 -1 Max 0.
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71M6533/G/H and 71M6534/H Data Sheet 6.4.5 FDS_6533_6534_004 Battery Monitor The LSB values do not include the 8-bit left shift at CE input. Table 74: Battery Monitor Performance Specifications (BME = 1) Parameter Load Resistor LSB Value Condition [M40MHZ, M26MHZ] = [00], [10], or [11] [M40MHZ, M26MHZ] = [01] FIR_LEN=0 FIR_LEN=1 FIR_LEN=2 FIR_LEN=0 FIR_LEN=1 FIR_LEN=2 (L=138) (L=288) (L=384) (L=186) (L=384) (L=588) Offset Error 6.4.6 Min 27 (-10%) (-10%) -200 Typ 45 -48.7 -5.35 -2.26 -19.8 -2.
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FDS_6533_6534_004 6.4.8 71M6533/G/H and 71M6534/H Data Sheet 2.5 V Voltage Regulator Unless otherwise specified, the load = 5 mA. Table 77: 2.5 V Voltage Regulator Performance Specifications Parameter V2P5 V2P5 load regulation Condition Iload = 0 Iload = 0 mA to 5 mA Iload = 5 mA, reduce V3P3 until V2P5 drops 200 mV RESET=0, iload=0 Voltage overhead V3P3SYS-V2P5 PSSR ∆V2P5/∆V3P3 6.4.9 Min 2.3 Typ 2.5 Max 2.
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71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 6.4.12 LCD DAC Table 81: LCD DAC Performance Specifications Parameter VLCD Voltage VLCD = V 3P3 ⋅ (1 − 0.059 ⋅ LCD _ DAC ) − 0.019V Condition Min 1 ≤ LCD_DAC ≤ 7 -10 Typ Max Unit +10 % 6.4.13 LCD Drivers The information in Table 82 applies to all COM and SEG pins with LCD_DAC[2:0] = 000.
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FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet 6.4.14 Temperature Sensor Table 83 shows the performance for the temperature sensor. The LSB values do not include the 8-bit left shift at CE input. Table 83: Temperature Sensor Performance Specifications Parameter Condition Nominal relationship: N(T) = Sn*(T-Tn) + Nn, Tn = 25ºC FIR_LEN=0 (L=138) [M40MHZ, M26MH] = FIR_LEN=1 (L=288) Nominal [00], [10], or [11] 2 FIR_LEN=2 (L=384) Sensitivity (Sn) 3 FIR_LEN=0 (L=186) L   S n = −0.
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71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 6.4.15 VREF and VBIAS Table 84 shows the performance specifications for VREF and VBIAS. Unless otherwise specified, VREF_DIS = 0. Table 84: VREF Performance Specifications Parameter Condition VREF output voltage, VREF(22) VREF chop step VREF power supply sensitivity ΔVREF / ΔV3P3A V3P3A = 3.0 to 3.6 V VREF_DIS = 1, VREF = 1.3 to 1.
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FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet 6.4.16 ADC Converter, V3P3A Referenced Table 85 shows the performance specifications for the ADC converter, V3P3A referenced. For this data, FIR_LEN=2, [M40MHZ, M26MHZ]=[00], unless stated otherwise, VREF_DIS=0. LSB values do not include the 8-bit left shift at the CE input.
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71M6533/G/H and 71M6534/H Data Sheet 6.5 6.5.1 FDS_6533_6534_004 Timing Specifications Flash Memory Table 86: Flash Memory Timing Specifications Parameter Flash Read Pulse Width Flash write cycles Flash data retention Flash data retention Flash byte writes between page or mass erase operations Write Time per Byte Page Erase (1024 bytes) Mass Erase 6.5.
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FDS_6533_6534_004 6.5.5 71M6533/G/H and 71M6534/H Data Sheet SPI Slave Port (MISSION Mode) Table 90: SPI Slave Port (MISSION Mode) Timing Parameter tSPIcyc PCLK cycle time tSPILead Enable lead time tSPILag Enable lag time tSPIW PCLK pulse width: High Low Condition Ignore if PCLK is low when PCSZ falls.
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71M6533/G/H and 71M6534/H Data Sheet 6.6 FDS_6533_6534_004 Typical Performance Data 6.6.1 Accuracy over Current Figure 49 shows meter accuracy over current for various line frequencies. Figure 50 shows meter accuracy over current at various load angles. 6533/34 Wh Performance, Equation 5, 45 Hz, 55 Hz, 65 Hz - 240 V - 0° Phase Angle 0.5 0.4 0.3 45 Hz 55 Hz 0.2 65 Hz % Error 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0.1 1 10 100 1000 Current (A rms) Figure 49: Wh Accuracy (0.
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FDS_6533_6534_004 6.6.2 71M6533/G/H and 71M6534/H Data Sheet Accuracy over Temperature With digital temperature compensation enabled, the temperature characteristics of the reference voltage (VREF) are compensated to within ±40 PPM/°C for the 71M6533/71M6534 and within ±15 PPM/°C for the 71M6533H/71M6534H. 6.7 6.7.1 Package Outline Drawings 71M6533 (100-Pin LQFP) Controlling dimensions are in mm. 15.7(0.618) 16.3(0.641) 1 15.7(0.618) 16.3(0.641) Top View 14.000 +/- 0.200 MAX. 1.600 1.50 +/- 0.
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71M6533/G/H and 71M6534/H Data Sheet 6.7.2 FDS_6533_6534_004 71M6534/6534H (120-Pin LQFP) Controlling dimensions are in mm. 16.000 +/- 0.200 14.000 +/- 0.100 7.000 8.000 120 16.000 +/- 0.200 8.000 14.000 +/- 0.100 7.000 1 13.950 +/- 0.100 MAX. 1.600 1.400 +/- 0.050 0.180 +/- 0.050 0.400 0.100 +/- 0.050 0.600 +/- 0.
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FDS_6533_6534_004 6.
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71M6533/G/H and 71M6534/H Data Sheet 71M6534/71M6534H Pinout (120-Pin LQFP) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Teridian 71M6534/ 71M6534H 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 SEG59/DIO39 SEG58/DIO38 SEG57/DIO37 SEG56/DIO36 GNDD RESET V2P5 VBAT RX SEG48/DIO28 SEG31/DIO11 SEG30/DIO10 SEG29/DIO9/YPULSE SEG28/DIO8/XPULSE SEG41/DIO21 SEG40/DIO20 SEG39/DIO19 SEG27/DIO7/RPULSE SEG26/DIO6/WPULSE SEG25/DIO5/SDATA
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FDS_6533_6534_004 6.9 71M6533/G/H and 71M6534/H Data Sheet Pin Descriptions Pins marked with an asterisk (e.g. V2*) are only available on the 71M6534. 6.9.1 Power and Ground Pins Table 91: Power and Ground Pins Name GNDA GNDD Type P P Circuit – – V3P3A P – V3P3SYS P – V3P3D O 13 VBAT P 12 V2P5 O 10 6.9.2 Description Analog ground: This pin should be connected directly to the ground plane. Digital ground: This pin should be connected directly to the ground plane.
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71M6533/G/H and 71M6534/H Data Sheet 6.9.
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FDS_6533_6534_004 E_RXTX/SEG9 E_RST/SEG11 E_TCLK/SEG10 71M6533/G/H and 71M6534/H Data Sheet I/O I/O O 1, 4, 5 1, 4, 5 4, 5 ICE_E I 2 CKTEST/SEG19, MUXSYNC/SEG7 O 4, 5 TMUXOUT O 4 OPT_RX/DIO1 I/O 3, 4 OPT_TX/DIO2 I/O 3, 4 RESET I 2 RX I 3 TX O 4 TEST I 7 PB I 3 Multi-use pins, configurable as either emulator port pins (when ICE_E pulled high) or LCD SEG drivers (when ICE_E tied to GND). ICE enable.
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71M6533/G/H and 71M6534/H Data Sheet 6.9.
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FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet 7 Ordering Information PART 71M6533 71M6533H 71M6533G* 71M6533 71M6533H 71M6533G* PINPACKAGE VREF TRIM DEVIATION** 100 LQFP (Lead(Pb)free) ±40 ±15 ±40 ±40 ±15 ±40 FLASH ORDERING SIZE PACKAGE NUMBER (KB) 128 71M6533-IGT/F 128 Bulk 71M6533H-IGT/F 256 71M6533G-IGT/F 128 71M6533-IGTR/F Tape and 128 71M6533H-IGTR/F reel 256 71M6533G-IGTR/F 71M6534 ±40 128 120 LQFP 71M6534H ±15 256 (Lead(Pb)71M6534 ±40 128 free) 71M6534H ±15 256 *Future product—contac
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71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004 Appendix A: Acronyms AFE AMR ANSI CE DIO DSP FIR I2C ICE IEC MPU PLL RMS SFR SOC SPI TOU UART 128 Analog Front End Automatic Meter Reading American National Standards Institute Compute Engine Digital I /O Digital Signal Processor Finite Impulse Response Inter-IC Bus In-Circuit Emulator International Electrotechnical Commission Microprocessor Unit (CPU) Phase-locked loop Root Mean Square Special Function Register System on Chip Serial Peripheral Inte
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FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet Appendix B: Revision History REVISION NUMBER 2 REVISION DATE 2/12 1.2 August 3, 2010 Rev 2 DESCRIPTION 1) Added Guaranteed By Design notes to the Electrical Specifications. 2) Added explanation on NV properties of RTCA_ADJ[ ] and PREG/QREG[ ] and corrected entries in Table 54. 3) Added note that transitions to BROWNOUT mode must be avoided during page erase operations. 4) Added note in Application Section (3.
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71M6533/G/H and 71M6534/H Data Sheet REVISION NUMBER REVISION DATE FDS_6533_6534_004 DESCRIPTION 12) 13) 14) 15) 16) 17) 18) 19) precautions for switching between modes and factory programming of the first 6 flash addresses.. Figure 25, Figure 26 and Figure 27: Corrected name for PSDI and PSDO signals. Section 2.5.2 Wake on Timer (page 66): Updated description. Section 3.
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FDS_6533_6534_004 REVISION NUMBER 1.1 REVISION DATE November 9, 2009 1.0 March 6, 2009 71M6533/G/H and 71M6534/H Data Sheet DESCRIPTION Changes and corrections: 1) Stated < 0.1% for accuracy for both H and non-H parts over 2000:1 range on title page. 2) Added STOP and IDLE bits in description of PCOM SFR. 3) Consolidated spelling of RTCA_ADJ. 4) Added explanation for Figure 18. 5) Completely revised section 2.5.2 (Wake on Timer). 6) Improved description of hysteresis in Application Section (3.11).
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71M6533/G/H and 71M6534/H Data Sheet 132 Rev 2