Datasheet

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet
Rev 2 105
5.3.13 CE Flow Diagrams
Figure 45 through Figure 47 show the data flow through the CE in simplified form. Functions not shown
include delay compensation, sample interpolation, scaling and the processing of meter equations.
Figure 45: CE Data Flow: Multiplexer and ADC
Figure 46: CE Data Flow: Scaling, Gain Control, Intermediate Variables
F
CLK
= 4.9152MHz
VREFmultiplexer
F
S
= 2184 Hz
Per channel
ΔΣ
mod
FIR
de-multiplexer
F
S
= 2184 Hz
Per channel
IA_RAW
IA
VB
VA
IB
IC
VC
IB_RAW
VA_RAW
VB_RAW
IC_RAW
VC_RAW
ID
ID_RAW
IA_RAW
VA_RAW
OFFSET
NULL
PHASE
COMP
GAIN_ADJ
CAL_IA
x x x
LPF
PHADJ_A
W0
OFFSET
NULL
x x
x
LPF
CAL_VA
90°
VAR0
IA
V0
F0
Generator
F0
F0
F0
x
...other phases