Datasheet
FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet
Rev 2 43
On reset or power-up, all DIO pins are inputs until they are configured for the desired direction under
MPU control. The pin function can be configured by the I/O RAM bits LCD_BITMAPn. Setting
LCD_BITMAPn = 1 configures the pin for LCD, setting LCD_BITMAPn = 0 configures it for DIO.
Once a pin is configured as DIO, it can be configured independently as an input or output with the
DIO_DIR bits or the LCD_SEGn registers. Input and output data are written to or read from the pins using
SFR registers P0, P1, and P2.
Table 39 through
Table 42 shows all the DIO pins with their configuration, direction control and data registers. Table
entries marked with an asterisk and grayed are applicable to the 71M6534 only.
Table 39: Data/Direction Registers and Internal Resources for DIO 1-15
DIO
PB
1
2
3
4
5
6
7
8
9
10
11
12*
13
14
15
LCD Segment
–
–
–
–
24
25
26
27
28
29
30
31
32*
33
34
35
71M6533 Pin #
97
91
3
17
60
61
62
63
67
68
69
70
–
44
29
30
71M6534 Pin #
114
109
3
22
70
71
72
73
77
78
79
80
120
50
35
36
Configuration (DIO
or LCD segment)
Always DIO
0
1
2
3
4
5
6
7
0*
1
2
3
LCD_BITMAP[31:24]
LCD_BITMAP[39:32]
Data Register
0
1
2
3
4
5
6
7
0
1
2
3
4*
5
6
7
DIO0 = P0 (SFR 0x80)
DIO1 = P1 (SFR 0x90)
Direction Register
0 = input, 1 = output
–
1
2
3
4
5
6
7
0
1
2
3
4*
5
6
7
DIO_DIR0 (SFR 0xA2)
DIO_DIR1 (SFR 0x91)
Internal Resources
Configurable
Y Y Y Y Y Y Y Y Y Y Y Y – – – –
Table 40: Data/Direction Registers and Internal Resources for DIO 16-30
DIO
16
17
18
19
20
21
22*
23
24
25
26
27
28*
29
30
–
LCD Segment
36
37
38
39
40
41
42*
43
44
45
46
47
48*
49
50
–
71M6533 Pin #
33
12
13
64
65
66
–
54
46
43
42
41
–
32
35
–
71M6534 Pin #
39
17
18
74
75
76
115
64
52
49
48
47
81
38
41
Configuration (DIO
or LCD segment)
4
5
6
7
0
1
2*
3
4
5
6
7
0*
1
2
–
LCD_BITMAP[39:32]
LCD_BITMAP[47:40]
LCD_BITMAP[55:48]
Data Register
0
1
2
3
4
5
6*
7
0
1
2
3
4*
5
6
–
DIO2 = P2 (SFR 0xA0)
DIO3 = P3 (SFR 0xB0)
Direction Register
0 = input, 1 = output
0
1
2
3
4
5
6*
7
LCD_SEG44[3]
LCD_SEG45[3]
LCD_SEG46[3]
LCD_SEG47[3]
LCD_SEG48[3]*
LCD_SEG49[3]
LCD_SEG50[3]
DIO_DIR2 (SFR 0xA1)