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ManualsBrandsMAXIM INTEGRATED ManualsPMICsPMIC - power monitoring Three-phase, Neutral LQFP 120 Surface-mount
51525354555657585960
71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004
56 Rev 2
2.2 System Timing Summary
Figure 19 summarizes the timing relationships between the input MUX states, the CE_BUSY signal and
the two serial output streams. In this example, MUX_DIV[3:0] = 6 and FIR_LEN[1:0] = 1. The duration of
each MUX frame is (M40MHZ/M26MHZ = 00, 10, or 11 assumed):
• 1 + MUX_DIV[3:0] * 1, if FIR_LEN[1:0] = 0 (138 CE cycles), complete MUX frame = 7 CK32 cycles
• 1 + MUX_DIV[3:0] * 2, if FIR_LEN[1:0] = 1 (288 CE cycles) , complete MUX frame = 13 CK32 cycles
• 1 + MUX_DIV[3:0] * 3, if FIR_LEN[1:0] = 2 (384 CE cycles) , complete MUX frame = 19 CK32 cycles
An ADC conversion will always consume an integer number of CK32 clocks. Following this is a single
CK32 cycle where the bandgap voltage is allowed to recover from the change in CROSS.
Figure 19: Timing Relationship between ADC MUX and Compute Engine
Each CE program pass begins when the ADC0 conversion (slot 0, as defined by SLOT0_SEL) begins.
Depending on the length of the CE program, it may continue running until the end of the last conversion.
CE opcodes are constructed to ensure that all CE code passes consume exactly the same number of
cycles. The result of each ADC conversion is inserted into the XRAM when the conversion is complete.
The CE code is written to tolerate sudden changes in ADC data. The exact clock count when each ADC
value is loaded into RAM is shown in Figure 19.
Figure 20 shows that the serial data stream, RTM, begins transmitting at the beginning of state S. RTM,
consisting of 140 CK cycles, will always finish before the next code pass starts.
FLAG
RTM DATA 0 (32 bits)
0 1
0 1
0 1
0 1
FLAG
FLAG
FLAG
CK32
MUX_SYNC
CKTEST
TMUXOUT/RTM
LSB
LSB
SIGN
SIGN
LSB
SIGN
30 31 30 31
30
31
30 31
LSB
SIGN
RTM DATA 1 (32 bits)
RTM DATA 2 (32 bits)
RTM DATA 3 (32 bits)
Figure 20: RTM Output Format