Datasheet

71M6541D/F/G and 71M6542F/G Data Sheet
Rev 4 115
Name Location
Rst
Wk Dir Description
FL_BANK
SFR B6
01 01 R/W
Flash Bank Selection (71M6541G and 71M6542G only)
The program memory of the 71M6541G/71M6542G consists of a fixed lower
bank of 32 KB, addressable at 0x0000 to 0x7FFF plus an upper banked area
of 32 KB, addressable at 0x8000 to 0xFFFF. The I/O RAM register FL_BANK
is used to switch one of four memory banks of 32 KB each into the address
range from 0x8000 to 0xFFFF. Note that when FL_BANK = 0, the upper bank
is the same as the lower bank.
FL_BANK[1:0]
Address Range for
Lower Bank
(0x0000-0x7FFF)
Address Range for
Upper Bank
(0x8000-0xFFFF)
00
0x0000-0x7FFF
0x00000-0x07FFF
01
0x0000-0x7FFF
0x08000-0x0FFFF
10
0x0000-0x7FFF
0x10000-0x17FFF
11
0x0000-0x7FFF
0x18000-0x1FFFF
FLSH_ERASE[7:0]
SFR 94[7:0] 0 0 W
Flash Erase Initiate
FLSH_ERASE
is used to initiate either the Flash Mass Erase cycle or the Flash
Page Erase cycle. Specific patterns are expected for FLSH_ERASE in order
to initiate the appropriate Erase cycle.
(default = 0x00).
0x55 = Initiate Flash Page Erase cycle. Must be proceeded by a write to
FLSH_PGADR[5:0] (SFR 0xB7[7:2]).
0xAA = Initiate Flash Mass Erase cycle. Must be proceeded by a write to
FLSH_MEEN and the ICE port must be enabled.
Any other pattern written to
FLSH_ERASE
has no effect.
FLSH_MEEN
SFR B2[1] 0 0 W
Mass Erase Enable
0 = Mass Erase disabled (default).
1 = Mass Erase enabled.
Must be re-written for each new Mass Erase cycle.
FLSH_PEND
SFR B2[3] 0 0 R
Indicates that a timed flash write is pending. If another flash write is attempted,
it is ignored.
FLSH_PGADR[5:0]
SFR B7[7:2] 0 0 W
Flash Page Erase Address
FLSH_PGADR[5:0] – Flash Page Address (page 0 thru 63) that is erased during
the Page Erase cycle. (default = 0x00).
Must be re-written for each new Page Erase cycle.