Datasheet

71M6541D/F/G and 71M6542F/G Data Sheet
118 Rev 4
Name Location
Rst
Wk Dir Description
LCD_SEG0[5:0]
to
LCD_SEG15[5:0]
2410[5:0] to
241F[5:0]
0 – R/W
SEG Data for SEG0 through SEG15. DIO data for these pins is in SFR
space.
LCD_SEGDIO16[5:0]
to
LCD_SEGDIO45[5:0]
2420[5:0] to
243D[5:0]
0 – R/W
SEG and DIO data for SEGDIO16 through SEGDIO45. If configured as DIO,
bit 1 is direction (1 is output, 0 is input), bit 0 is data, and the other bits are
ignored.
LCD_SEG46[5:0]
to
LCD_SEG50[5:0]
243E[5:0] to 2442[5:0] 0 – R/W
SEG data for SEG46 through SEG50. These pins cannot be configured as
DIO.
LCD_SEGDIO51[5:0]
to
LCD_SEGDIO55[5:0]
2443[5:0] to 2447[5:0] 0 – R/W
SEG and DIO data for SEGDIO51 through SEGDIO55. If configured as DIO,
bit 1 is direction (1 is output, 0 is input), bit 0 is data, and the other bits are
ignored.
SEGDIO52 through SEDIO54 are available only on the 71M6542F/G.
LCD_VMODE[1:0]
2401[7:6] 00 00 R/W
Specifies how VLCD is generated. See 2.5.8.4 for the definition of V3P3L.
LCD_VMODE
Description
11
External VLCD
10
LCD boost and LCD DAC enabled
01
LCD DAC enabled
00
No boost and no DAC. VLCD=V3P3L.
LCD_Y
2400[2] 0 – R/W
LCD Blink Frequency (ignored if blink is disabled).
1 = 1 Hz, 0 = 0.5 Hz
LKPADDR[6:0]
2887[6:0]
0
0
R/W
The address for reading and writing the RTC lookup RAM
LKPAUTOI
2887[7] 0 0 R/W
Auto-increment flag. When set, LKPADDR auto-increments every time
LKP_RD or LKP_WR is pulsed. The incremented address can be read at
LKPADDR[6:0].
LKPDAT[7:0]
2888[7:0]
0
0
R/W
The data for reading and writing the RTC lookup RAM.
LKP_RD
LKP_WR
2889[1]
2889[0]
0
0
0
0
R/W
R/W
Strobe bits for the RTC lookup RAM read and write. When set, the
LKPADDR[6:0] field and LKPDAT register is used in a read or write
operation. When a strobe is set, it stays set until the operation completes, at
which time the strobe is cleared and LKPADDR[6:0] is incremented if the
LKPAUTOI bit is set.