Datasheet

71M6541D/F/G and 71M6542F/G Data Sheet
Rev 4 59
OPT
_TXINV
UART
1
_
TX
MOD
EN DUTY
SEGDIO
51
/
OPT_TX
OPT_TXMOD
OPT_FDC
OPT_TXE[
1:
0
]
0
2
V3P3
Internal
A B
OPT_TXMOD=
0
OPT
_
TXMOD
=
1
,
OPT
_
FDC
=
2
(
25
%)
B
A
1/
38kHz
1
2
3
DIO
51
WPULSE
VARPULSE
SEG
51
LCD
_
MAP
[
51
]
1
0
SEGDIO
55
/
OPT
_RX
SEG
55
LCD
_
MAP
[
55
]
1
0
DIO
55
1
0
OPT
_
RXDIS
UART1_RX
DIO
5
SEGDIO
5
/
TX
2
SEG
5
1
0
LCD
_
MAP
[
5
]
OPT_BB
0
0
1
1
Figure 19: Optical Interface (UART1)
2.5.8 Digital I/O and LCD Segment Drivers
2.5.8.1 General Information
The 71M6541D/F/G and 71M6542F/G combine most DIO pins with LCD segment drivers. Each
SEG/DIO pin can be configured as a DIO pin or as a segment (SEG) driver pin.
On reset or power-up, all DIO pins are DIO inputs (except for SEGDIO0-15, see caution note below) until
they are configured as desired under MPU control. The pin function can be configured by the I/O RAM
registers LCD_MAPn (0x2405 – 0x240B). Setting the bit corresponding to the pin in LCD_MAPn to 1
configures the pin for LCD, setting LCD_MAPn to 0 configures it for DIO.
After reset or power up, pins SEGDIO0 through SEGDIO15 are initially DIO outputs, but are
disabled by PORT_E = 0 (I/O RAM 0x270C[5]) to avoid unwanted pulses during reset. After
configuring pins SEGDIO0 through SEGDIO15 the MPU must enable these pins by setting
PORT_E.
Once a pin is configured as DIO, it can be configured independently as an input or output. For SEGDIO0
to SEGDIO15, this is done with the SFR registers P0 (SFR 0x80), P1 (SFR 0x90), P2 (SFR 0xA0) and P3
(SFR 0xB0), as shown in Table 48 (71M6541D/F/G) and Table 52 (71M6542F/G).
The PB pin is a dedicated digital input and is not part of the SEGDIO system.
The CE features pulse counting registers and each pulse counter interrupt output is internally
routed to the pulse interrupt logic. Thus, no routing of pulse signals to external pins is required in
order to generate pulse interrupts. See interrupt source No. 2 in Figure 16.
A 3-bit configuration word, I/O RAM register DIO_Rn (I/O RAM 0x2009[2:0] through 0x200E[6:4]) can be
used for pins SEGDIO2 through SEGDIO11 (when configured as DIO) and PB to individually assign an
internal resource such as an interrupt or a timer control (DIO_RPB[2:0], I/O RAM 0x2450[2:0], configures
the PB pin). This way, DIO pins can be tracked even if they are configured as outputs. Table 47 lists
the internal resources which can be assigned using DIO_R2[2:0] through DIO_R11[2:0] and DIO_RPB[2:0].
If more than one input is connected to the same resource, the resources are combined using a logical OR.