Datasheet
71M6541D/F/G and 71M6542F/G Data Sheet
Rev 4
Table 33: Interrupt Enable and Flag Bits
Interrupt Enable
Interrupt Flag
Interrupt Description
Name
Location
Name
Location
EX0
SFR 0xA8[[0]
IE0
SFR 0x88[1]
External interrupt 0
EX1
SFR 0xA8[2]
IE1
SFR 0x88[3]
External interrupt 1
EX2
SFR 0xB8[1]
IEX2
SFR 0xC0[1]
External interrupt 2
EX3
SFR 0xB8[2]
IEX3
SFR 0xC0[2]
External interrupt 3
EX4
SFR 0xB8[3]
IEX4
SFR 0xC0[3]
External interrupt 4
EX5
SFR 0xB8[4]
IEX5
SFR 0xC0[4]
External interrupt 5
EX6
SFR 0xB8[5]
IEX6
SFR 0xC0[5]
External interrupt 6
EX_XFER
EX_RTC1S
EX_RTC1M
EX_RTCT
EX_SPI
EX_EEX
EX_XPULSE
EX_YPULSE
EX_WPULSE
EX_VPULSE
0x2700[0]
0x2700[1]
0x2700[2]
0x2700[4]
0x2701[7]
0x2700[7]
0x2700[6]
0x2700[5]
0x2701[6]
0x2701[5]
IE_XFER
IE_RTC1S
IE_RTC1M
IE_RTCT
IE_SPI
IE_EEX
IE_XPULSE
IE_YPULSE
IE_WPULSE
IE_VPULSE
SFR 0xE8[0]
SFR 0xE8[1]
SFR E0x8[2]
SFR 0xE8[4]
SFR 0xF8[7]
SFR 0xE8[7]
SFR 0xE8[6]
SFR 0xE8[5]
SFR 0xF8[6]
SFR 0xF8[5]
XFER_BUSY interrupt (int 6)
RTC_1SEC interrupt (int 6)
RTC_1MIN interrupt (int 6)
RTC_T alarm clock interrupt (int 6)
SPI interrupt
EEPROM interrupt
CE_XPULSE interrupt (int 2)
CE_YPULSE interrupt (int 2)
CE_WPULSE interrupt (int 2)
CE_VPULSE interrupt (int 2)
Interrupt Priority Level Structure
All interrupt sources are combined in groups, as shown in Table 34.
Table 34: Interrupt Priority Level Groups
Group Group Members
0
External interrupt 0
Serial channel 1 interrupt
1
Timer 0 interrupt
External interrupt 2
2
External interrupt 1
External interrupt 3
3
Timer 1 interrupt
External interrupt 4
4
Serial channel 0 interrupt
External interrupt 5
5
—
External interrupt 6
Each group of interrupt sources can be programmed individually to one of four priority levels (as shown in
Table 35) by setting or clearing one bit in the SFR interrupt priority register IP0 (SFR 0xA9) and one in IP1
(SFR 0xB9) (Table 36). If requests of the same priority level are received simultaneously, an internal polling
sequence as shown in Table 37 determines which request is serviced first.
Changing interrupt priorities while interrupts are enabled can easily cause software defects. It is best
to set the interrupt priority registers only once during initialization before interrupts are enabled.
Table 35: Interrupt Priority Levels
IP1
[x]
IP0
[x]
Priority Level
0
0
Level 0 (lowest)
0
1
Level 1
1
0
Level 2
1
1
Level 3 (highest)