Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsPMICsPMIC - power monitoring Single phase LQFP 64 Surface-mount

19-5376; Rev 4; 3/14

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71M6541D/F/G and 71M6542F/G

Energy Meter ICs

GENERAL DESCRIPTION

The 71M6541D/71M6541F/71M6541G/71M6542F/71M6542G are

4th-generation single-phase metering SoCs with a 5MHz 8051-

compatible MPU core, low-power RTC with digital temperature

compensation, flash memory, and LCD driver. Our Single Converter

Technology® with a 22-bit delta-sigma ADC, three or four analog

inputs, digital temperature compensation, precision voltage reference,

and a 32-bit computation engine (CE) supports a wide range of

metering applications with very few external components.

The 71M6541/2 devices support optional interfaces to the 71M6x01

series of isolated sensors, which offer BOM cost reduction, immunity

to magnetic tamper, and enhanced reliability. Other features include

an SPI interface, advanced power management, ultra-low-power

operation in active and battery modes, 3/5KB shared RAM and

32/64/128KB of flash memory that can be programmed in the field

with code and/or data during meter operation and the ability to drive

up to six LCD segments per SEG driver pin. High processing and

sampling rates combined with differential inputs offer a powerful

metering platform for residential meters.

A complete array of code development tools, demonstration code,

and reference designs enable rapid development and certification of

meters that meet all ANSI and IEC electricity metering standards

worldwide.

MPU

RTC

TIMERS

IAP

IBP

XIN

XOUT

COM0...5

3A V3P3SYS

VBAT

VBAT_RTC

SEG

GNDA GNDD

SEG/DIO

DIO

ICE

LINE

NEUTRAL

LOAD

8888.8888

PULSES,

DIO

AMR

POWER FAULT

COMPARATOR

MODUL-

ATOR

SERIAL PORTS

OSCILLATOR/

PLL

MUX and ADC

LCD DRIVER

DIO, PULSES

COMPUTE

ENGINE

FLASH

MEMORY

RAM

32 kHz

REGULATOR

Shunt

POWER SUPPLY

71M6541D/F/G

TEMPERATURE

SENSOR

VREF

BATTERY

PWR MODE

CONTROL

WAKE

-UP

NEUTRAL

C or µWire

EEPROM

IAN

IBN

RTC

BATTERY

V3P3D

BATTERY

MONITOR

SPI INTERFACE

HOST

LCD DISPLAY

Resistor Divider

Pulse

Trans-

former

71M6xx1

Shunt

LINE

Note:

This system is referenced to LINE

11/5/2010

FEATURES

• 0.1% Typical Accuracy Over 2000:1 Current

Range

• Exceeds IEC 62053/ANSI C12.20 Standards

• Two Current Sensor Inputs with Selectable

Differential Mode

• Selectable Gain of 1 or 8 for One Current Input to

Support Shunts

• High-Speed Wh/VARh Pulse Outputs with

Programmable Width

• 32KB Flash, 3KB RAM (71M6541D)

• 64KB Flash, 5KB RAM (71M6541F/42F)

• 128KB Flash, 5KB RAM (71M6541G/42G)

• Up to Four Pulse Outputs with Pulse Count

• Four-Quadrant Metering

• Digital Temperature Compensation:

- Metrology Compensation

- Accurate RTC for TOU Functions with

Automatic Temperature Compensation for

Crystal in All Power Modes

• Independent 32-Bit Compute Engine

• 46-64Hz Line Frequency Range with the Same

Calibration

• Phase Compensation (±10°)

• Three Battery-Backup Modes:

- Brownout Mode (BRN)

- LCD Mode (LCD)

- Sleep Mode (SLP)

• Wake-Up on Pin Events and Wake-On Timer

• 1µA in Sleep Mode

• Flash Security

• In-System Program Update

• 8-Bit MPU (80515), Up to 5 MIPS

• Full-Speed MPU Clock in Brownout Mode

• LCD Driver:

- Up to 6 Commons/Up to 56 Pins

• 5V LCD Driver with DAC

• Up to 51 Multifunction DIO Pins

• Hardware Watchdog Timer (WDT)

• I

C/MICROWIRE® EEPROM Interface

• SPI Interface with Flash Program Capability

• Two UARTs for IR and AMR

• IR LED Driver with Modulation

• Industrial Temperature Range

• 64-Pin (71M6541D/F/G) and 100-pin

(71M6542F/G) Lead(Pb)-Free LQFP Package

Single Converter Technology is a registered trademark of Maxim Integrated Products, Inc.

MICROWIRE is a registered trademark of National Semiconductor Corp.

Summary of content (166 pages)

PAGE 1
71M6541D/F/G and 71M6542F/G Energy Meter ICs GENERAL DESCRIPTION FEATURES The 71M6541D/71M6541F/71M6541G/71M6542F/71M6542G are 4th-generation single-phase metering SoCs with a 5MHz 8051compatible MPU core, low-power RTC with digital temperature compensation, flash memory, and LCD driver.
PAGE 2
71M6541D/F/G and 71M6542F/G Data Sheet Table of Contents 1 2 3 2 Introduction ....................................................................................................................................... 10 Hardware Description ....................................................................................................................... 11 2.1 Hardware Overview ................................................................................................................... 11 2.
PAGE 3
71M6541D/F/G and 71M6542F/G Data Sheet 3.3 4 5 Fault and Reset Behavior .......................................................................................................... 85 3.3.1 Events at Power-Down .................................................................................................. 85 3.3.2 IC Behavior at Low Battery Voltage ............................................................................... 86 3.3.3 Reset Sequence .....................................................
PAGE 4
71M6541D/F/G and 71M6542F/G Data Sheet 6 Electrical Specifications................................................................................................................. 139 6.1 Absolute Maximum Ratings ..................................................................................................... 139 6.2 Recommended External Components ..................................................................................... 140 6.3 Recommended Operating Conditions..............................
PAGE 5
71M6541D/F/G and 71M6542F/G Data Sheet Figures Figure 1: IC Functional Block Diagram ......................................................................................................... 9 Figure 2. 71M6541D/F/G AFE Block Diagram (Local Sensors) ................................................................. 12 Figure 3. 71M6541D/F/G AFE Block Diagram with 71M6x01 .................................................................... 13 Figure 4. 71M6542F/G AFE Block Diagram (Local Sensors) ...........
PAGE 6
71M6541D/F/G and 71M6542F/G Data Sheet Tables Table 1. Required CE Code and Settings for Local Sensors...................................................................... 15 Table 2. Required CE Code and Settings for 71M6x01 Isolated Sensor ................................................... 16 Table 3: ADC Input Configuration .............................................................................................................. 17 Table 4: Multiplexer and ADC Configuration Bits ..................
PAGE 7
1M6541D/F/G and 71M6542F/G Data Sheet Table 53: Data/Direction Registers for SEGDIO16 to SEGDIO31 (71M6542F/G) ..................................... 64 Table 54: Data/Direction Registers for SEGDIO32 to SEGDIO45 (71M6542F/G) ..................................... 64 Table 55: Data/Direction Registers for SEGDIO51 to SEGDIO55 (71M6542F/G) ..................................... 64 Table 56: LCD_VMODE[1:0] Configurations ...........................................................................................
PAGE 8
71M6541D/F/G and 71M6542F/G Data Sheet Table 106: PLL Performance Specifications ............................................................................................. 145 Table 107: LCD Driver Performance Specifications ................................................................................. 146 Table 108: LCD Driver Performance Specifications1 ................................................................................ 147 Table 109: VREF Performance Specifications.....................
PAGE 9
71M6541D/F/G and 71M6542F/G Data Sheet V3P3A VREF IAP IAN IBP IBN VLCD GNDA GNDD V3P3SYS ∆Σ AD CONVERTER VBIAS MUX and PREAMP VBIAS VLCD Voltage Boost FIR V3P3A - V3P3D + VREF VA VB* VREF VBAT MUX MUX CTRL CROSS Voltage Regulator CK32 XIN XOUT MCK PLL RTCLK (32KHz) Oscillator CK32 32KHz 32 KHz DIV ADC 4.9 MHZ CKADC VDD CKFIR 4.9 MHz 22 2.5V to logic CLOCK GEN CK_4X MUX LCD_GEN CKMPU_2x WPULSE STRT VARPULSE CKCE < 4.
PAGE 10
71M6541D/F/G and 71M6542F/G Data Sheet 1 Introduction This data sheet covers the 71M6541D (32KB), 71M6541F (64KB), 71M6541G (128KB), 71M6542F (64KB), and 71M6542G (128KB) fourth-generation energy measurement SoCs. The term “71M654x” is used when discussing a device feature or behavior that is applicable to all four part numbers. The appropriate part number is indicated when a device feature or behavior is being discussed that applies only to a specific part number.
PAGE 11
71M6541D/F/G and 71M6542F/G Data Sheet 2 Hardware Description 2.1 Hardware Overview The 71M6541D/F/G and 71M6542F/G single-chip energy meter ICs integrate all primary functional blocks required to implement a solid-state residential electricity meter.
PAGE 12
71M6541D/F/G and 71M6542F/G Data Sheet transformers (CTs) and their corresponding signal conditioning circuits can be characterized and their correction factors can be programmed to produce electricity meters with exceptional accuracy over the industrial temperature range. One of the two internal UARTs is adapted to support an Infrared LED with internal drive and sense configuration and can also function as a standard UART. The optical output can be modulated at 38 kHz.
PAGE 13
71M6541D/F/G and 71M6542F/G Data Sheet Figure 3 shows the 71M6541D/F/G multiplexer interface with one local and one remote resistive shunt sensor. As seen in Figure 3, when a remote isolated shunt sensor is connected via the 71M6x01, the samples associated with this current channel are not routed to the multiplexer, and are instead transferred digitally to the 71M6541D/F/G via the digital isolation interface and are directly stored in CE RAM.
PAGE 14
71M6541D/F/G and 71M6542F/G Data Sheet Figure 5 shows the 71M6542F/G multiplexer interface with one local and one remote resistive shunt sensor. As seen in Figure 5, when a remote isolated shunt sensor is connected via the 71M6x01, the samples associated with this current channel are not routed to the multiplexer, and are instead transferred digitally to the 71M6542F/G via the digital isolation interface and are directly stored in CE RAM.
PAGE 15
71M6541D/F/G and 71M6542F/G Data Sheet The performance of the IAP-IAN pins can be enhanced by enabling a pre-amplifier with a fixed gain of 8, using the I/O RAM control bit PRE_E (I/O RAM 0x2704[5]). When PRE_E = 1, IAP-IAN become the inputs to the 8x pre-amplifier, and the output of this amplifier is supplied to the multiplexer. The 8x amplification is useful when current sensors with low sensitivity, such as shunt resistors, are used. With PRE_E set, the IAP-IAN input signal amplitude is restricted to 31.
PAGE 16
71M6541D/F/G and 71M6542F/G Data Sheet Table 2.
PAGE 17
71M6541D/F/G and 71M6542F/G Data Sheet processed with locally connected sensors, as shown in Figure 3. When using one local and one remote sensor (Figure 5), the multiplexer sequence is also as shown in Figure 7. For both multiplexer sequences shown in Figure 6 and Figure 7, the frame duration is 13 CK32 cycles (where CK32 = 32768 Hz), therefore, the resulting sample rate is 32768 Hz / 13 = 2520.6 Hz. Table 3 summarizes the various AFE input configurations.
PAGE 18
71M6541D/F/G and 71M6542F/G Data Sheet Multiplexer advance, FIR initiation and chopping of the ADC reference voltage (using the internal CROSS signal, see 2.2.7 Voltage References) are controlled by the internal MUX_CTRL circuit. Additionally, MUX_CTRL launches each pass of the CE through its code. Conceptually, MUX_CTRL is clocked by CK32, the 32768 Hz clock from the PLL block.
PAGE 19
71M6541D/F/G and 71M6542F/G Data Sheet Delay compensation and other functions in the CE code require the settings for MUX_DIV[3:0], MUXx_SEL[3:0], RMT_E, FIR_LEN[1:0], ADC_DIV and PLL_FAST to be fixed for a given CE code. Refer to Table 1 and Table 2 for the settings that are applicable to the 71M6541D/F/G and 71M6542F/G. Table 4 summarizes the I/O RAM registers used for configuring the multiplexer, signals pins, and ADC.
PAGE 20
71M6541D/F/G and 71M6542F/G Data Sheet the current. The delay compensation implemented in the CE aligns the voltage samples with their corresponding current samples by first delaying the current samples by one full sample interval (i.e., 360o), then routing the voltage samples through the all-pass filter, thus delaying the voltage samples by 360o - θ, resulting in the residual phase error between the current and its corresponding voltage of θ – Ф.
PAGE 21
71M6541D/F/G and 71M6542F/G Data Sheet A Vinp B A Vinn B A + G - Voutp B A Voutn B CROSS Figure 8: General Topology of a Chopped Amplifier It is assumed that an offset voltage Voff appears at the positive amplifier input.
PAGE 22
71M6541D/F/G and 71M6542F/G Data Sheet 2.2.8 71M6x01 Isolated Sensor Interface (Remote Sensor Interface) 2.2.8.1 General Description Non-isolating sensors, such as shunt resistors, can be connected to the inputs of the 71M654x via a combination of a pulse transformer and a 71M6x01 IC (a top-level block diagram of this sensor interface is shown in Figure 36). The 71M6x01 receives power directly from the 71M654x via a pulse transformer and does not require a dedicated power supply circuit.
PAGE 23
71M6541D/F/G and 71M6542F/G Data Sheet Table 5. RCMD[4:0] Bits Associated TMUXRn Command Phase Selector RCMD[4:2] RCMD[1:0] Control Field --000 Invalid 00 Invalid IBP-IBN TMUXRB [2:0] 001 Command 1 01 010 Command 2 011 Reserved 100 Reserved 101 Invalid 110 Reserved 111 Reserved Notes: 1. Only two codes of RCMD[4:2] (SFR 0xFC[4:2]) are relevant for normal operation. These are RCMD[4:2] = 001 and 010. Codes 000 and 101 are invalid and will be ignored if used.
PAGE 24
71M6541D/F/G and 71M6542F/G Data Sheet Name Address RST WAKE Default Default PERR_RD PERR_WR SFR FC[6] SFR FC[5] 0 0 CHOPR[1:0] 2709[7:6] 00 00 TMUXRB[2:0] 270A[2:0] RMT_RD[15:8] 2602[7:0] RMT_RD[7:0] 2603[7:0] 000 000 0 0 R/W Description itself is in RCMD[4:2]. The 71M654x sets these bits to indicate that a parity error on the isolated sensor has been deR/W tected. Once set, the bits are remembered until they are cleared by the MPU. The CHOP settings for the isolated sensors.
PAGE 25
71M6541D/F/G and 71M6542F/G Data Sheet The XRAM can be accessed by the FIR filter block, the RTM circuit, the CE, and the MPU. Assigned time slots are reserved for FIR and MPU, respectively, to prevent bus contention for XRAM data access by the CE. The MPU reads and writes the XRAM shared between the CE and MPU as the primary means of data communication between the two processors. Table 3 shows the CE addresses in XRAM allocated to analog inputs from the AFE.
PAGE 26
71M6541D/F/G and 71M6542F/G Data Sheet equivalent to 203 ns) and contains a leading flag bit. See Figure 10 for the RTM output format. RTM is low when not in use. Figure 11 summarizes the timing relationships between the input MUX states, the CE_BUSY signal, and the RTM serial output stream. In this example, MUX_DIV[3:0] = 4 (I/O RAM 0x2100[7:4]) and FIR_LEN[1:0] = 10 (I/O RAM 0x210C[1]), (384), resulting in 4 ADC conversions. An ADC conversion always consumes an integer number of CK32 clocks.
PAGE 27
71M6541D/F/G and 71M6542F/G Data Sheet 2.3.6 Pulse Generators The 71M6541D/F/G and 71M6542F/G provide four pulse generators, VPULSE, WPULSE, XPULSE and YPULSE, as well as hardware support for the VPULSE and WPULSE pulse generators. The pulse generators can be used to output CE status indicators, SAG for example, to DIO pins. All pulses can be configured to generate interrupts to the MPU. The polarity of the pulses may be inverted with control bit PLS_INV (I/O RAM 0x210C[0]).
PAGE 28
71M6541D/F/G and 71M6542F/G Data Sheet If the FIFO is enabled (i.e., PLS_INTERVAL[7:0] ≠ 0), hardware also provides a maximum pulse width feature in control register PLS_MAXWIDTH[7:0] (I/O RAM 0x210A) . By default, WPULSE and VPULSE are negative pulses (i.e., low level pulses, designed to sink current through an LED).
PAGE 29
71M6541D/F/G and 71M6542F/G Data Sheet IB channel is a 71M6x01 isolated sensor, the sample data does not pass through the 71M6541D/F/G multiplexer, as seen in Figure 3. In this case, the sample is taken during the second half of the multiplexer cycle and the data is directly stored in the corresponding CE RAM location as indicated in Figure 3.
PAGE 30
71M6541D/F/G and 71M6542F/G Data Sheet IB VA IA 30.5 µs 122.07 µs 122.07 µs 122.07 µs Multiplexer Frame (13 x 30.518 µs = 396.7 µs -> 2520.6 Hz) MUX_DIV[3:0] = 3 Conversions Settle CK32 (32768 Hz) MUX STATE 0 S 2 1 S Figure 14: Samples from Multiplexer Cycle (MUX_DIV[3:0] = 3) VB IB VA IA 91.5 µs 91.5 µs 91.5 µs 30.5 µs 91.5 µs Multiplexer Frame (13 x 30.
PAGE 31
71M6541D/F/G and 71M6542F/G Data Sheet 2.4 80515 MPU Core The 71M6541D/F/G and 71M6542F/G include an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one clock cycle. Using a 4.9 MHz clock results in a processing throughput of 4.9 MIPS. The 80515 architecture eliminates redundant bus states and implements parallel execution of fetch and execution phases.
PAGE 32
71M6541D/F/G and 71M6542F/G Data Sheet To change the slot assignments established by MUXn_SEL[3:0], first set MUX_DIV[3:0] to zero, then change the MUXn_SEL[3:0] slot assignments, and finally set MUX_DIV[3:0] to the number of active MUX frame slots. The 80515 writes into external data memory when the MPU executes a MOVX @Ri,A or MOVX @DPTR,A instruction.
PAGE 33
71M6541D/F/G and 71M6542F/G Data Sheet DPTR1 is useful for copy routines, where it can make the inner loop of the routine two instructions faster compared to the reloading of DPTR from registers. Any interrupt routine using DPTR1 must save and restore DPS, DPTR and DPTR1, which increases stack usage and slows down interrupt latency. By selecting the R80515 core in the Keil compiler project settings and by using the compiler directive “MODC2”, dual data pointers are enabled in certain library routines.
PAGE 34
71M6541D/F/G and 71M6542F/G Data Sheet Bit Addressable Hex/ Bin X000 S0CON P1(DIO4:7) TCON P0 (DIO0:3) 98 90 88 80 2.4.3 Byte Addressable X001 S0BUF TMOD SP X010 IEN2 DPS TL0 DPL X011 S1CON TL1 DPH X100 S1BUF ERASE TH0 DPL1 X101 S1RELL TH1 DPH1 X110 X111 EEDATA EECTRL CKCON PCON Bin/ Hex 9F 97 8F 87 Generic 80515 Special Function Registers Table 13 shows the location, description and reset or power-up value of the generic 80515 SFRs.
PAGE 35
71M6541D/F/G and 71M6542F/G Data Sheet Name T2CON PSW WDCON A B Address (Hex) 0xC8 0xD0 0xD8 0xE0 0xF0 Reset value Description (Hex) 0x00 Polarity for INT2 and INT3 0x00 Program Status Word 0x00 Baud Rate Control Register (only WDCON[7] bit used) 0x00 Accumulator 0x00 B Register Page 43 35 37 35 35 Accumulator (ACC, A, SFR 0x E0): ACC is the accumulator register. Most instructions use the accumulator to hold the operand.
PAGE 36
71M6541D/F/G and 71M6542F/G Data Sheet Port Registers: SEGDIO0 through SEGDIO15 are controlled by Special Function Registers P0, P1, P2 and P3 as shown in Table 15. Above SEGDIO15, the LCD_SEGDIOn[ ] registers in I/O RAM are used.
PAGE 37
71M6541D/F/G and 71M6542F/G Data Sheet 2.4.4 Instruction Set All instructions of the generic 8051 microcontroller are supported. A complete list of the instruction set and of the associated op-codes is contained in the 71M654X Software User’s Guide (SUG). 2.4.5 UARTs The 71M6541D/F/G and 71M6542F/G include a UART (UART0) that can be programmed to communicate with a variety of AMR modules and other external devices. A second UART (UART1) is connected to the optical port, as described in 2.5.
PAGE 38
71M6541D/F/G and 71M6542F/G Data Sheet 8-bit output data. 7-bit serial modes without parity can be simulated by setting bit 7 to a constant 1. 8-bit serial modes with parity can be simulated by setting and reading the 9th bit, using the control bits TB80 (S0CON[3]) and TB81 (S1CON[3]) in the S0CON (SFR 0x98) and S1CON (SFR 0x9B) registers for transmit and RB81 bit in S1CON[2] for receive operations.
PAGE 39
71M6541D/F/G and 71M6542F/G Data Sheet Table 20: The S1CON (UART1) Register (SFR 0x9B) Bit S1CON[7] Symbol SM Function Sets the baud rate and mode for UART1. SM 0 1 S1CON[5] S1CON[4] S1CON[3] SM21 REN1 TB81 S1CON[2] RB81 S1CON[1] TI1 S1CON[0] RI1 Mode A B Description 9-bit UART 8-bit UART Baud Rate variable variable Enables the inter-processor communication feature. If set, enables serial reception. Cleared by software to disable reception. The 9th transmitted data bit in Mode A.
PAGE 40
71M6541D/F/G and 71M6542F/G Data Sheet Table 22: Timers/Counters Mode Description M1 0 M0 0 Mode Mode 0 0 1 1 0 Mode 1 Mode 2 1 1 Mode 3 Function 13-bit Counter/Timer mode with 5 lower bits in the TL0 or TL1 (SFR 0x8A or SFR 0x8B) register and the remaining 8 bits in the TH0 or TH1 (SFR 0x8C or SFR 0x8D) register (for Timer 0 and Timer 1, respectively). The 3 high order bits of TL0 and TL1 are held at zero. 16-bit Counter/Timer mode. 8-bit auto-reload Counter/Timer.
PAGE 41
71M6541D/F/G and 71M6542F/G Data Sheet Table 25: The TCON Register Bit Functions (SFR 0x88) Bit TCON[7] TCON[6] TCON[5] TCON[4] TCON[3] TCON[2] TCON[1] TCON[0] 2.4.7 Symbol Function TF1 The Timer 1 overflow flag is set by hardware when Timer 1 overflows. This flag can be cleared by software and is automatically cleared when an interrupt is processed. TR1 Timer 1 run control bit. If cleared, Timer 1 stops. TF0 Timer 0 overflow flag set by hardware when Timer 0 overflows.
PAGE 42
71M6541D/F/G and 71M6542F/G Data Sheet • The interrupt priority registers: IP0 and IP1 (see Table 36). Table 26: The IEN0 Bit Functions (SFR 0xA8) Bit IEN0[7] IEN0[6] IEN0[5] IEN0[4] IEN0[3] IEN0[2] IEN0[1] IEN0[0] Symbol EAL – – ES0 ET1 EX1 ET0 EX0 Function EAL = 0 disables all interrupts. Not used. Not used. ES0 = 0 disables serial channel 0 interrupt. ET1 = 0 disables timer 1 overflow interrupt. EX1 = 0 disables external interrupt 1: DIO status change ET0 = 0 disables timer 0 overflow interrupt.
PAGE 43
71M6541D/F/G and 71M6542F/G Data Sheet Table 30: The T2CON Bit Functions (SFR 0xC8) Bit T2CON[7] T2CON[6] Symbol – I3FR T2CON[5] I2FR T2CON[4:0] – Function Not used. Polarity control for external interrupt 3: CE_BUSY 0 = falling edge. 1 = rising edge. Polarity control for external interrupt 2: XPULSE, YPULSE, WPULSE and VPULSE 0 = falling edge. 1 = rising edge. Not used.
PAGE 44
71M6541D/F/G and 71M6542F/G Data Sheet External MPU Interrupts The seven external interrupts are the interrupts external to the 80515 core, i.e., signals that originate in other parts of the 71M654x, for example the CE, DIO, RTC, or EEPROM interface. The external interrupts are connected as shown in Table 32. The polarity of interrupts 2 and 3 is programmable in the MPU via the I3FR and I2FR bits in T2CON (SFR 0xC8). Interrupts 2 and 3 should be programmed for falling sensitivity (I3FR = I2FR = 0).
PAGE 45
71M6541D/F/G and 71M6542F/G Data Sheet Table 33: Interrupt Enable and Flag Bits Interrupt Enable Name EX0 EX1 EX2 EX3 EX4 EX5 EX6 EX_XFER EX_RTC1S EX_RTC1M EX_RTCT EX_SPI EX_EEX EX_XPULSE EX_YPULSE EX_WPULSE EX_VPULSE Interrupt Flag Location SFR 0xA8[[0] SFR 0xA8[2] SFR 0xB8[1] SFR 0xB8[2] SFR 0xB8[3] SFR 0xB8[4] SFR 0xB8[5] 0x2700[0] 0x2700[1] 0x2700[2] 0x2700[4] 0x2701[7] 0x2700[7] 0x2700[6] 0x2700[5] 0x2701[6] 0x2701[5] Name IE0 IE1 IEX2 IEX3 IEX4 IEX5 IEX6 IE_XFER IE_RTC1S IE_RTC1M IE_RTCT IE_SPI IE_
PAGE 46
71M6541D/F/G and 71M6542F/G Data Sheet Table 36: Interrupt Priority Registers (IP0 and IP1) Register Address Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 IP0 IP1 SFR 0xA9 SFR 0xB9 – – – – IP0[5] IP1[5] IP0[4] IP1[4] IP0[3] IP1[3] IP0[2] IP1[2] IP0[1] IP1[1] Bit 0 (LSB) IP0[0] IP1[0] External interrupt 0 Serial channel 1 interrupt Timer 0 interrupt External interrupt 2 External interrupt 1 External interrupt 3 Timer 1 interrupt External interrupt 4 Serial channel 0 interrupt External in
PAGE 47
71M6541D/F/G and 71M6542F/G Data Sheet Figure 16: Interrupt Structure Rev 4 47
PAGE 48
71M6541D/F/G and 71M6542F/G Data Sheet 2.5 On-Chip Resources 2.5.1 Physical Memory 2.5.1.1 Flash Memory The device includes 128KB (71M6541G, 71M6542G), 64KB (71M6542F, 71M6541F) or 32KB (71M6541D) of on-chip flash memory. The flash memory primarily contains MPU and CE program code. It also contains images of the CE RAM and I/O RAM. On power-up, before enabling the CE, the MPU copies these images to their respective locations.
PAGE 49
71M6541D/F/G and 71M6542F/G Data Sheet The page erase sequence is: • • Write the page address to FLSH_PGADR[5:0] (SFR 0xB7[7:2]). Write the pattern 0x55 to the FLSH_ERASE register (SFR 0x94). Program Security When enabled, the security feature limits the ICE to global flash erase operations only. All other ICE operations are blocked. This guarantees the security of the user’s MPU and CE program code.
PAGE 50
71M6541D/F/G and 71M6542F/G Data Sheet While operating in SPI Flash Mode (SFM), SPI single-byte transactions are used to write to FL_BANK[1:0]. During an SPI single-byte transaction, SPI_CMD[1:0] will overwrite the contents of FL_BANK[1:0]. This will allow for access of the entire 128 KB Flash memory while operating in SFM on the 71M6541G/71M6542G.
PAGE 51
71M6541D/F/G and 71M6542F/G Data Sheet Table 41: Clock System Summary Clock Derived From OSC Crystal MCK Crystal/PLL CKCE MCK CKADC MCK CKMPU MCK CKICE MCK CKOPTMOD MCK CK32 MCK 2.5.4 Fixed Frequency or Range Function Controlled by PLL_FAST=1 PLL_FAST=0 32.768 kHz – Crystal clock 19.660800 MHz 6.291456 MHz PLL_FAST Master clock (600*CK32) (192*CK32) 4.9152 MHz 1.5728 MHz – CE clock 1.572864 MHz, 4.9152 MHz, ADC_DIV ADC clock 2.4576 MHz 0.786432 MHz 4.9152 MHz … 1.
PAGE 52
71M6541D/F/G and 71M6542F/G Data Sheet Table 42: RTC Control Registers Name RTCA_ADJ[6:0] RTC_P[16:14] RTC_P[13:6] RTC_P[5:0] RTC_Q[1:0] Location 2504[6:0] 289B[2:0] 289C[7:0] 289D[7:2] 289D[1:0] Rst 64 4 0 0 0 Wk – 4 0 0 0 RTC_RD 2890[6] 0 0 RTC_WR 2890[7] 0 0 RTC_FAIL 2890[4] 0 0 RTC_SBSC[7:0] 2892[7:0] Dir Description R/W Register for analog RTC frequency adjustment. R/W Registers for digital RTC adjustment. 0x0FFBF ≤ RTC_P ≤ 0x10040 R/W Register for digital RTC adjustment.
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71M6541D/F/G and 71M6542F/G Data Sheet  32768 ⋅ 8  4 ⋅ RTC_P + RTC_Q = floor  + 0.5  −6  1 + ∆ ⋅10  Conversely, the amount of ppm shift for a given value of 4RTC_P+RTC_Q is: ∆ (𝑝𝑝𝑚) = � 32768 ∙ 8 − 1� 106 4 ∗ 𝑅𝑇𝐶𝑃 + 𝑅𝑇𝐶𝑄 For example, for a shift of -988 ppm, 4⋅RTC_P + RTC_Q = 262403 = 0x40103. RTC_P = 0x10040, and RTC_Q = 0x03. The default values of RTC_P and RTC_Q, corresponding to zero adjustment, are 0x10000 and 0x0, respectively.
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71M6541D/F/G and 71M6542F/G Data Sheet Referring to Figure 17, the table lookup method uses the 10-bits plus sign-bit value in STEMP[10:0] rightshifted by two bits to obtain an 8-bit plus sign value (i.e., NV RAM Address = STEMP/4). A limiter ensures that the resulting look-up address is in the 6-bit plus sign range of -64 to +63 (decimal). The 8-bit NV RAM content pointed to by the address is added as a 2’s complement value to 0x40000, the nominal value of 4*RTC_P + RTC_Q. Refer to 2.5.4.
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71M6541D/F/G and 71M6542F/G Data Sheet STEMP[10:0] (10+S) (decimal) Temp ( C) (Equation) 0 22.00 1 22.33 2 22.65 3 22.98 4 23.31 5 23.64 6 23.96 7 … 252 24.29 … 104.40 253 104.73 254 105.06 255 105.39 o STEMP[10:0]>>2 (8+S) (decimal) Limiter Output (6+S) (decimal) Temp ( C) (LU Table) 0 0 22.65 1 1 23.96 … … … 63 63 105.
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71M6541D/F/G and 71M6542F/G Data Sheet 2.5.5 71M654x Temperature Sensor The 71M654x includes an on-chip temperature sensor for determining the temperature of its bandgap reference. The primary use of the temperature data is to determine the magnitude of compensation required to offset the thermal drift in the system for the compensation of current, voltage and energy measurement and the RTC. See 4.7 Metrology Temperature Compensation on page 97. Also see 2.5.4.4 RTC Temperature Compensation on page 53.
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71M6541D/F/G and 71M6542F/G Data Sheet Name Location Rst Wk Dir TEMP_BAT 28A0[4] 0 – R/W TEMP_START 28B4[6] 0 – R/W TEMP_PWR 28A0[6] 0 – R/W TEMP_BSEL 28A0[7] 0 – R/W 0 – R/W TEMP_TEST[1:0] 2500[1:0] STEMP[10:3] STEMP[2:0] 2881[7:0] 2882[7:5] BSENSE[7:0] 2885[7:0] – – 2704[3] 0 0 BCURR Description Causes VBAT to be measured whenever a temperature measurement is performed. TEMP_PER[2:0] must be zero in order for TEMP_START to function.
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71M6541D/F/G and 71M6542F/G Data Sheet Refer to the 71M6xxx Data Sheet for information on reading the VCC sensor in the 71M6x01 devices. 2.5.7 UART and Optical Interface The 71M6541D/F/G and 71M6542F/G provide two asynchronous interfaces, UART0 and UART1. Both can be used to connect to AMR modules, user interfaces, etc., and also support a mechanism for programming the on-chip flash memory. Referring to Figure 19, UART1 includes an interface to implement an IR/optical port.
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71M6541D/F/G and 71M6542F/G Data Sheet Internal SEG55 DIO55 UART1_RX 1 1 0 0 OPT_RXDIS UART1_TX 0 DIO5 1 EN OPT_TXMOD OPT_FDC 0 2 0 V3P3 SEGDIO51/ OPT_TX 1 DIO51 B DUTY LCD_MAP[55] 3 WPULSE MOD A OPT_TXINV SEG51 VARPULSE SEGDIO55/ OPT_RX 0 LCD_MAP[51] 1 OPT_TXE[1:0] SEG5 2 1 0 SEGDIO5/TX2 1 LCD_MAP[5] OPT_BB OPT_TXMOD=1, OPT_FDC=2 (25%) OPT_TXMOD=0 A B 1/38kHz Figure 19: Optical Interface (UART1) 2.5.8 Digital I/O and LCD Segment Drivers 2.5.8.
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71M6541D/F/G and 71M6542F/G Data Sheet Table 47: Selectable Resources using the DIO_Rn[2:0] Bits Resource Selected for SEGDIOn or PB Pin Value in DIO_Rn[2:0] 0 None 1 Reserved 2 T0 (counter0 clock) 3 T1 (counter1 clock) 4 High priority I/O interrupt (INT0) Low priority I/O interrupt (INT1) 5 Note: Resources are selectable only on SEGDIO2 through SEGDIO11 and the PB pin. See Table 48 (71M6541D/F/G) and Table 52 (71M6542F/G). When driving LEDs, relay coils etc.
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71M6541D/F/G and 71M6542F/G Data Sheet 2.5.8.2 Digital I/O for the 71M6541D/F/G A total of 32 combined SEG/DIO pins plus 5 SEG outputs are available for the 71M6541D/F/G.
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71M6541D/F/G and 71M6542F/G Data Sheet Table 49: Data/Direction Registers for SEGDIO19 to SEGDIO27 (71M6541D/F/G) SEGDIO – – – 19 20 21 22 23 24 25 26 27 – – – – Pin # – – – 16 15 14 13 12 11 10 9 8 – – – – 3 4 5 6 7 0 1 2 3 – – – – – – LCD_MAP[23:19] (I/O RAM 0x2409) LCD_MAP[27:24] (I/O RAM 0x2408) – – – 19 20 21 22 23 24 25 26 27 – – – – LCD_SEGDIO19[5:0] to LCD_SEGDIO27[5:0] (I/O RAM 0x2423[5:0] to 0x242C[5:0]) – – – 19 20 21 22 23 24 25 26 27 – – – – LCD_SEGDIO19[0] to
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71M6541D/F/G and 71M6542F/G Data Sheet 2.5.8.3 Digital I/O for the 71M6542F/G A total of 55 combined SEG/DIO pins are available for the 71M6542D/F.
PAGE 64
71M6541D/F/G and 71M6542F/G Data Sheet Table 53: Data/Direction Registers for SEGDIO16 to SEGDIO31 (71M6542F/G) SEGDIO Pin # 16 28 Configuration: 0 = DIO, 1 = LCD 0 SEG Data Register 17 27 18 25 20 23 21 22 22 21 23 20 24 19 25 18 26 17 27 16 28 11 29 10 30 9 31 8 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 LCD_MAP[23:16] (I/O RAM 0x2409) LCD_MAP[31:24] (I/O RAM 0x2408) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 LCD_SEGDIO16[5:0] to LCD_SEGDIO31[5:0] (I/O RAM 0x2420[5:0] to 0x242F[5:0]) 16 17 18
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71M6541D/F/G and 71M6542F/G Data Sheet 2.5.8.4 LCD Drivers The LCD drivers are grouped into up to six commons (COM0 – COM5) and up to 56 segment drivers. The LCD interface is flexible and can drive 7-segment digits, 14-segments digits or enunciator symbols. A voltage doubler and a contrast DAC generate VLCD from either VBAT or V3P3SYS, depending on the V3P3SYS voltage.
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71M6541D/F/G and 71M6542F/G Data Sheet The LCD system has the ability to drive up to six segments per SEG driver. If the display is configured with six back planes, the 6-way multiplexing compresses the number of SEG pins required to drive a display and therefore enhance the number of DIO pins available to the application. Refer to the LCD_MODE[2:0] field (I/O RAM 0x2400[6:4]) settings (Table 57) for the different LCD multiplexing choices. If 5-state multiplexing is selected, SEGDIO27 is converted to COM4.
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71M6541D/F/G and 71M6542F/G Data Sheet Table 57 shows all I/O RAM registers that control the operation of the LCD interface.
PAGE 68
71M6541D/F/G and 71M6542F/G Data Sheet The LCD bias may be compensated for temperature using the LCD_DAC[4:0] field (I/O RAM 0x240D[4:0]). The bias may be adjusted from 1.4 V below the 3.3 V supply (V3P3SYS in MSN mode and VBAT in BRN and LCD modes). When the LCD_DAC[4:0] field is set to 000, the DAC is bypassed and powered down. This can be used to reduce current in LCD mode.
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71M6541D/F/G and 71M6542F/G Data Sheet LCD Drivers (71M6541D/F/G) With a maximum of 35 LCD driver pins available, the 71M6541D/F/G is capable of driving up to 6 x 35 = 210 pixels of an LCD display when using the 6 x multiplex mode. At eight pixels per digit, this corresponds to 26 digits. LCD segment data is written to the LCD_SEGn[5:0] I/O RAM registers as described in 2.5.8.2 and 2.5.8.3. SEG46 through SEG50 cannot be configured as DIO pins.
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71M6541D/F/G and 71M6542F/G Data Sheet LCD Drivers (71M6542F/G) With a maximum of 56 LCD driver pins available, the 71M6542D/F is capable of driving up to 6 x 56 = 336 pixels of an LCD display when using the 6 x multiplex mode. At eight pixels per digit, this corresponds to 42 digits. LCD segment data is written to the LCD_SEGn[5:0] I/O RAM registers as described in 2.5.8.3 Digital I/O for the . SEG46 through SEG50 cannot be configured as DIO pins.
PAGE 71
M6541D/F/G and 71M6542F/G Data Sheet Table 60: EECTRL Bits for 2-pin Interface Status Bit 7 6 5 4 Reset State 0 0 1 Polarity Description ERROR BUSY RX_ACK Read/ Write R R R Positive Positive Positive TX_ACK R 1 Positive 1 when an illegal command is received. 1 when serial data bus is busy. 1 indicates that the EEPROM sent an ACK bit. 1 indicates that an ACK bit has been sent to the EEPROM.
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71M6541D/F/G and 71M6542F/G Data Sheet Control Bit 4 3:0 Read/ Description Write RD Indicates that EEDATA (SFR 0x9E) is to be filled with data from EEPROM. W Specifies the number of clocks to be issued. Allowed values are 0 through 8. If RD=1, CNT bits of data are read MSB first, and right CNT[3:0] justified into the low order bits of EEDATA. If RD=0, CNT bits are sent W MSB first to the EEPROM, shifted out of the MSB of EEDATA. If CNT[3:0] is zero, SDATA simply obeys the HiZ bit.
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71M6541D/F/G and 71M6542F/G Data Sheet EECTRL Byte Written INT5 not issued CNT Cycles (0 shown) Write -- No HiZ EECTRL Byte Written Write -- HiZ INT5 not issued CNT Cycles (0 shown) SCLK (output) SCLK (output) SDATA (output) SDATA (output) D7 SDATA output Z SDATA output Z (LoZ) (HiZ) BUSY (bit) BUSY (bit) Figure 25: 3-Wire Interface.
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71M6541D/F/G and 71M6542F/G Data Sheet When SPI_CSZ rises, SPI command bytes that are not of the form x000 0000 update the SPI_CMD (SFR 0xFD) register and then cause an interrupt to be issued to the MPU. The exception is if the transaction was a single byte. In this case, the SPI_CMD byte is always updated and the interrupt issued. SPI_CMD is not cleared when SPI_CSZ is high. The SPI port supports data transfers up to 10 Mb/s.
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71M6541D/F/G and 71M6542F/G Data Sheet SERIAL READ 16 bit Address Status Byte 8 bit CMD DATA[ADDR] DATA[ADDR+1] Extended Read . . . (From Host) SPI_CSZ 0 15 16 A0 C7 23 31 24 32 39 40 D0 D7 47 (From Host) SPI_CK (From Host) SPI_DI A15 A14 A1 C6 C5 C0 HI Z (From 6543) SPI_DO SERIAL WRITE x ST7 16 bit Address ST6 ST5 ST0 D7 D6 DATA[ADDR] Status Byte 8 bit CMD D1 D6 D1 D0 DATA[ADDR+1] (From Host) SPI_CSZ Extended Write . . .
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71M6541D/F/G and 71M6542F/G Data Sheet Table 64: SPI Registers Name EX_SPI SPI_CMD Location 2701[7] SFR FD[7:0] Rst 0 – Wk 0 – Dir R/W R SPI_E 270C[4] 1 1 R/W IE_SPI SFR F8[7] 0 0 R/W SPI_SAFE 270C[3] 0 0 R/W SPI_STAT 2708[7:0] 0 0 R 76 Description SPI interrupt enable bit. SPI command. The 8-bit command from the bus master. SPI port enable bit. It enables the SPI interface on pins SEGDIO36 – SEGDIO39. SPI interrupt flag. Set by hardware, cleared by writing a 0.
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71M6541D/F/G and 71M6542F/G Data Sheet SPI Flash Mode (SFM) In normal operation, the SPI slave interface cannot read or write the flash memory. However, the 71M6541D/F/G and 71M6542F/G support an SPI Flash Mode (SFM) which facilitates initial programming of the flash memory. When in SFM mode, the SPI can erase, read, and write the flash memory. Other memory elements such as XRAM and I/O RAM are not accessible in this mode.
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71M6541D/F/G and 71M6542F/G Data Sheet SFM Details The following occurs upon entering SFM. • • • • • The CE is disabled. The MPU is halted. Once the MPU is halted it can only be restarted with a reset. This reset can be accomplished with the RESET pin, a watchdog reset, or by cycling power (without battery at the VBAT pin). The Flash control logic is reset in case the MPU was in the middle of a Flash write operation or Erase cycle.
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71M6541D/F/G and 71M6542F/G Data Sheet The TMUXOUT and TMUX2OUT pins may be used for diagnostics purposes during the product development cycle or in the production test. The RTC 1-second output may be used to calibrate the crystal oscillator. The RTC 4-second output provides higher precision for RTC calibration. RTCLK may also be used to calibrate the RTC. Table 65: TMUX[5:0] Selections Signal Name Description 1 RTCLK 9 WD_RST A CKMPU D V3AOK bit E V3OK bit 1B MUX_SYNC 32.
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71M6541D/F/G and 71M6542F/G Data Sheet 3 Functional Description 3.
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71M6541D/F/G and 71M6542F/G Data Sheet 3.2 Battery Modes Shortly after system power (V3P3SYS) is applied, the part is in mission mode (MSN mode). MSN mode means that the part is operating with system power and that the internal PLL is stable. This mode is the normal operating mode where the part is capable of measuring energy. When system power is not available, the 71M654x is in one of three battery modes: • • • BRN mode (brownout mode) LCD mode (LCD-only mode) SLP mode (sleep mode).
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71M6541D/F/G and 71M6542F/G Data Sheet Transitions from both LCD and SLP mode to BRN mode can be initiated by the following events: • • • • Wake-up timer timeout. Pushbutton (PB) is activated. A rising edge on SEGDIO4, or a high logic level on SEGDIO52 (71M6542F/G only) or SEGDIO55. Activity on the RX or OPT_RX pins. The MPU has access to a variety of registers that signal the event that caused the wake up. See 3.4 Wake Up Behavior for details.
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71M6541D/F/G and 71M6542F/G Data Sheet 3.2.1 BRN Mode In BRN mode, most non-metering digital functions are active (as shown in Table 67) including ICE, UART, EEPROM, LCD and RTC. In BRN mode, the PLL continues to function at the same frequency as MSN mode. It is up to the MPU to scale down the PLL (using PLL_FAST, I/O RAM 0x2200[4]) or the MPU frequency (using MPU_DIV[2:0], I/O RAM 0x2200[2:0]) in order to save power. From BRN mode, the MPU can choose to enter LCD or SLP modes.
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71M6541D/F/G and 71M6542F/G Data Sheet 3.2.3 SLP Mode When the V3P3SYS pin voltage drops below 2.8 VDC, the 71M654x enters BRN mode and the V3P3D pin obtains power from the VBAT pin instead of the V3P3SYS pin. Once in BRN mode, the MPU may invoke SLP mode by setting the SLEEP bit (I/O RAM 0x28B2[7]). The purpose of SLP mode is to consume the least amount power while still maintaining the RTC (Real Time Clock), temperature compensation of the RTC, and the non-volatile portions of the I/O RAM.
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71M6541D/F/G and 71M6542F/G Data Sheet 3.3 Fault and Reset Behavior 3.3.1 Events at Power-Down Power fault detection is performed by internal comparators that monitor the voltage at the V3P3A pin and also monitor the internally generated VDD pin voltage (2.5 VDC). The V3P3SYS and V3P3A pins must be tied together at the PCB level, so that the comparators, which are internally connected only to the V3P3A pin, are able to simultaneously monitor the common V3P3SYS and V3P3A pin voltage.
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71M6541D/F/G and 71M6542F/G Data Sheet 3.3.2 IC Behavior at Low Battery Voltage When system power is not present, the 71M6541D/F/G and 71M6542F/G rely on the VBAT pin for power. If the VBAT voltage is not sufficient to maintain VDD at 2.0 VDC or greater, the MPU cannot operate reliably. Low VBAT voltage can occur while the part is operating in BRN mode, or while it is dormant in SLP or LCD mode.
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71M6541D/F/G and 71M6542F/G Data Sheet There is no internal digital state that could deactivate the WDT. For debug purposes, however, the WDT can be disabled by raising the ICE_E pin to 3.3 VDC. In normal operation, the WDT is reset by periodically writing a one to the WD_RST control bit (I/O RAM 0x28B4[7]). The watchdog timer is also reset when the 71M654x wakes from LCD or SLP mode, and when ICE_E = 1. 3.
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71M6541D/F/G and 71M6542F/G Data Sheet Table 69: Wake Enables and Flag Bits Wake Enable Wake Flag De-bounce Description Name Location Name Location WAKE_ARM 28B2[5] WF_TMR 28B1[5] No Wake on Timer. EW_PB 28B3[3] WF_PB 28B1[3] Yes Wake on PB*. EW_RX 28B3[4] WF_RX 28B1[4] 2 µs Wake on either edge of RX. EW_DIO4 28B3[2] WF_DIO4 28B1[2] 2 µs Wake on SEGDIO4. EW_DIO52† 28B3[1] WF_DIO52 28B1[1] Yes Wake on SEGDIO52*.
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71M6541D/F/G and 71M6542F/G Data Sheet Table 70: Wake Bits Name Location RST WK Dir EW_DIO4 28B3[2] 0 – R/W EW_DIO52 28B3[1] 0 – R/W EW_DIO55 28B3[0] 0 – R/W WAKE_ARM 28B2[5] 0 – R/W EW_PB 28B3[3] 0 – R/W EW_RX 28B3[4] 0 – R/W WF_DIO4 28B1[2] 0 – R WF_DIO52 28B1[1] 0 – R WF_DIO55 28B1[0] 0 – R WF_TMR WF_PB WF_RX WF_RST WF_RSTBIT WF_ERST WF_CSTART WF_BADVDD 28B1[5] 28B1[3] 28B1[4] 28B0[6] 28B0[5] 28B0[3] 28B0[7] 28B0[2] 0 0 0 * * * * * – – – R R R Rev 4
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71M6541D/F/G and 71M6542F/G Data Sheet Table 71: Clear Events for WAKE flags Flag Wake on: Clear Events WF_TMR Timer expiration WAKE falls WF_PB PB pin high level WAKE falls WF_RX Either edge RX pin WAKE falls WF_DIO4 SEGDIO4 rising edge WAKE falls WF_DIO52 SEGDIO52 high level (71M6542F/G only) If OPT_RXDIS = 1 (I/O RAM 0x2457[2]), wake on SEGDIO55 high If OPT_RXDIS = 0 wake on either edge of OPT_RX WAKE falls WF_DIO55 WF_RST WF_RSTBIT WF_ERST WF_OVF WF_CSTART WAKE falls RESET pin drive
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71M6541D/F/G and 71M6542F/G Data Sheet 3.5 Data Flow and MPU/CE Communication The data flow between the Compute Engine (CE) and the MPU is shown in Figure 30. In a typical application, the 32-bit CE sequentially processes the samples from the voltage inputs on pins IA, VA, IB, etc., performing calculations to measure active power (Wh), reactive power (VARh), A2h, and V2h for four-quadrant metering.
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71M6541D/F/G and 71M6542F/G Data Sheet 4 Application Information 4.1 Connecting 5 V Devices All digital input pins of the 71M654x are compatible with external 5 V devices. I/O pins configured as inputs do not require current-limiting resistors when they are connected to external 5 V devices. 4.
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71M6541D/F/G and 71M6542F/G Data Sheet 4.3 71M6541D/F/G Using Local Sensors Figure 35 shows a 71M6541D/F/G configuration using locally connected current sensors. The IAP-IAN current channel may be directly connected to either a shunt resistor or a CT, while the IBP-IBN channel is connected to a CT and is therefore isolated. This configuration implements a single-phase measurement with tamper-detection using one current sensor to measure the neutral current.
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71M6541D/F/G and 71M6542F/G Data Sheet 4.4 71M6541D/F/G Using 71M6x01and Current Shunts Figure 36 shows a typical connection for one isolated and one non-isolated shunt sensor, using the 71M6x01 Isolated Sensor Interface. This configuration implements a single-phase measurement with tamper-detection using the second current sensor. This configuration can also be used to create a split phase meter (e.g., ANSI Form 2S).
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71M6541D/F/G and 71M6542F/G Data Sheet 4.5 71M6542F/G Using Local Sensors Figure 38 shows a 71M6542F/G configuration using locally connected current sensors. The IAP-IAN current channel may be directly connected to either a shunt resistor or a CT, while the IBP-IBN channel is connected to a CT and is therefore isolated. This configuration implements a dual-phase measurement utilizing Equation 2.
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71M6541D/F/G and 71M6542F/G Data Sheet 4.6 71M6542F/G Using 71M6x01 and Current Shunts Figure 38 shows a typical two-phase connection for the 71M6542F/G using one isolated and one nonisolated sensor. For best performance, the IAP-IAN current sensor input is configured for differential mode (i.e., DIFFA_E = 1, I/O RAM 0x210C[4]). The 71M6x01 Isolated Sensor Interface is used to isolate phase B.
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71M6541D/F/G and 71M6542F/G Data Sheet 4.7 Metrology Temperature Compensation 4.7.1 Voltage Reference Precision Since the VREF band-gap amplifier is chopper-stabilized, as set by the CHOP_E[1:0] (I/O RAM 0x2106[3:2]) control field, the dc offset voltage, which is the most significant long-term drift mechanism in the voltage references (VREF), is automatically removed by the chopper circuit. Both the 71M654x and the 71M6x01 feature chopper circuits for their respective VREF voltage reference.
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71M6541D/F/G and 71M6542F/G Data Sheet 4.7.3 Temperature Compensation for VREF with Local Sensors This section discusses metrology temperature compensation for the meter designs where local sensors are used, as shown in Figure 35 and Figure 37. In these configurations where all sensors are directly connected to the 71M654x, each sensor channel’s accuracy is affected by the voltage variation in the 71M654x VREF due to temperature.
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71M6541D/F/G and 71M6542F/G Data Sheet For VREF compensation, both the linear coefficient PPMC and the quadratic coefficient PPMC2, are determined as described in 4.7.2 Temperature Coefficients for the 71M654x. The compensation for the external error sources is accomplished by summing the PPMC value associated with VREF with the PPMC value associated with the external error source to obtain the final PPMC value for the sensor channel.
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71M6541D/F/G and 71M6542F/G Data Sheet • GAIN_ADJ2 provides compensation for the remotely connected IB shunt current sensor and compensates for the 71M6x01 VREF. The designer may optionally add compensation for the shunt connected to the 71M6x01 into the PPMC and PPMC2 coefficients for this channel.
PAGE 101
71M6541D/F/G and 71M6542F/G Data Sheet 4.9 Connecting Three-Wire EEPROMs µWire EEPROMs and other compatible devices should be connected to the DIO pins SEGDIO2/SDCK and SEGDIO3/SDATA, as described in 2.5.9 EEPROM Interface. 4.10 UART0 (TX/RX) The UART0 RX pin should be pulled down by a 10 kΩ resistor and additionally protected by a 100 pF ceramic capacitor, as shown in Figure 40. 71M654x RX 100 pF 10 k Ω TX RX TX Figure 40: Connections for UART0 4.
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71M6541D/F/G and 71M6542F/G Data Sheet V3P3SYS R1 71M654x OPT_RX 100 pF 10 kΩ Phototransistor V3P3SYS R2 LED OPT_TX Figure 41: Connection for Optical Components 4.12 Connecting the Reset Pin Even though a functional meter does not necessarily need a reset switch, it is useful to have a reset pushbutton for prototyping as shown in Figure 42, left side.
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71M6541D/F/G and 71M6542F/G Data Sheet 4.13 Connecting the Emulator Port Pins Even when the emulator is not used, small shunt capacitors to ground (22 pF) should be used for protection from EMI as illustrated in Figure 43. Production boards should have the ICE_E pin connected to ground.
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71M6541D/F/G and 71M6542F/G Data Sheet 4.14 Flash Programming 4.14.1 Flash Programming via the ICE Port Operational or test code can be programmed into the flash memory using either an in-circuit emulator or the Flash Programmer Module (TFP-2) available from Maxim. The flash programming procedure uses the E_RST, E_RXTX, and E_TCLK pins. 4.14.2 Flash Programming via the SPI Port It is possible to erase, read and program the flash memory of the SPI port. See 2.5.
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71M6541D/F/G and 71M6542F/G Data Sheet 5 Firmware Interface 5.1 I/O RAM Map –Functional Order In Table 74 and Table 75, unimplemented (U) and reserved (R) bits are shaded in light gray. Unimplemented bits are identified with a ‘U’. Unimplemented bits have no memory storage, writing them has no effect, and reading them always returns zero. Reserved bits are identified with an ‘R’, and must always be written with a zero.
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71M6541D/F/G and 71M6542F/G Data Sheet Name LCD_MAP5 LCD_MAP4 LCD_MAP3 LCD_MAP2 LCD_MAP1 LCD_MAP0 DIO_R5 DIO_R4 DIO_R3 DIO_R2 DIO_R1 DIO_R0 DIO0 DIO1 DIO2 INT1_E INT2_E WAKE_E SFMM SFMS Addr 2015 2016 2017 2018 2019 201A 201B 201C 201D 201E 201F 2020 2021 2022 2023 2024 2025 2026 2080 2081 Bit 7 Bit 6 U U U U U U U DIO_EEX[1:0] DIO_PW DIO_PV DIO_PX DIO_PY EX_EEX EX_XPULSE EX_SPI EX_WPULSE Bit 5 Bit 4 Bit 3 Bit 2 LCD_MAP[47:40] LCD_MAP[39:32] LCD_MAP[31:24] LCD_MAP[23:16] LCD_MAP[15:8] LCD_MAP[7:0] U U
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71M6541D/F/G and 71M6542F/G Data Sheet Table 75 lists bits and registers that may have to be accessed on a frequent basis. Reserved bits have lighter gray background, and non-volatile bits have a darker gray background.
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71M6541D/F/G and 71M6542F/G Data Sheet Name LCD_MAP4 LCD_MAP3 LCD_MAP2 LCD_MAP1 LCD_MAP0 LCD4 LCD_DAC SEGDIO0 … SEGDIO15 SEGDIO16 … SEGDIO45 SEGDIO46 … SEGDIO50 SEGDIO51 … SEGDIO55 Addr 2407 2408 2409 240A 240B 240C 240D 2410 … 241F 2420 … 243D 243E … 2442 2443 … 2447 DIO_R5 DIO_R4 DIO_R3 DIO_R2 DIO_R1 DIO_R0 DIO0 DIO1 DIO2 NV BITS RESERVED RESERVED TMUX 2450 2451 2452 2453 2454 2455 2456 2457 2458 108 2500 2501 2502 Bit 7 Bit 6 Bit 5 U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U
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71M6541D/F/G and 71M6542F/G Data Sheet Name Addr TMUX2 2503 RTC1 2504 71M6x01 Interface REMOTE2 2602 REMOTE1 2603 RBITS INT1_E 2700 INT2_E 2701 SECURE 2702 Analog0 2704 VERSION 2706 INTBITS 2707 FLAG0 SFR E8 FLAG1 SFR F8 STAT SFR F9 REMOTE0 SFR FC SPI1 SFR FD SPI0 2708 RCE0 2709 RTMUX 270A DIO3 270C NV RAM and RTC 2800NVRAMxx 287F WAKE 2880 STEMP1 2881 STEMP0 2882 BSENSE 2885 LKPADDR 2887 LKPDATA 2888 LKPCTRL 2889 RTC0 2890 RTC2 2892 Rev 4 Bit 7 U U Bit 6 U Bit 5 U Bit 4 Bit 3 Bit 2 TMUX2[4:0] Bit 1
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71M6541D/F/G and 71M6542F/G Data Sheet Name Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 U U RTC_SEC[5:0] RTC3 2893 U U RTC_MIN[5:0] RTC4 2894 U U U RTC_HR[4:0] RTC5 2895 U U U U U RTC_DAY[2:0] RTC6 2896 U U U RTC_DATE[4:0] RTC7 2897 U U U U RTC_MO[3:0] RTC8 2898 RTC_YR[7:0] RTC9 2899 U U U U U RTC_P[16:14] RTC10 289B RTC_P[13:6] RTC11 289C RTC_P[5:0] RTC_Q[1:0] RTC12 289D U U RTC_TMIN[5:0] RTC13 289E U U U RTC_THR[4:0] RTC14 289F OSC_COMP TEMP_BAT TBYTE_BUSY TEMP_PER[2:0] TEMP 28A0 TEMP_BSEL TEMP_P
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71M6541D/F/G and 71M6542F/G Data Sheet 5.2 I/O RAM Map – Alphabetical Order Table 76 lists I/O RAM bits and registers in alphabetical order. Bits with a write direction (W in column Dir) are written by the MPU into configuration RAM. Typically, they are initially stored in flash memory and copied to the configuration RAM by the MPU. Some of the more frequently programmed bits are mapped to the MPU SFR memory space. The remaining bits are mapped to the address space 0x2XXX.
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71M6541D/F/G and 71M6542F/G Data Sheet Name Location CHOPR[1:0] 2709[7:6] DIFFA_E DIFFB_E DIO_R2[2:0] DIO_R3[2:0] DIO_R4[2:0] DIO_R5[2:0] DIO_R6[2:0] DIO_R7[2:0] DIO_R8[2:0] DIO_R9[2:0] DIO_R10[2:0] DIO_R11[2:0] DIO_RPB[2:0] 210C[4] 210C[5] 2455[2:0] 2455[6:4] 2454[2:0] 2454[6:4] 2453[2:0] 2453[6:4] 2452[2:0] 2452[6:4] 2451[2:0] 2451[6:4] 2450[2:0] DIO_DIR[15:12] DIO_DIR[11:8] DIO_DIR[7:4] DIO_DIR[3:0] DIO[15:12] DIO[11:8] DIO[7:4] DIO[3:0] SFR B0[7:4] SFR A0[7:4] SFR 90[7:4] SFR 80[7:4] Rst Wk Dir
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71M6541D/F/G and 71M6542F/G Data Sheet Name DIO_PV DIO_PW DIO_PX DIO_PY EEDATA[7:0] EECTRL[7:0] Location 2457[6] 2457[7] 2458[7] 2458[6] SFR 9E SFR 9F Rst Wk 0 – 0 – 0 – 0 – 0 0 0 0 Dir R/W R/W R/W R/W R/W R/W Description Causes VARPULSE to be output on pin SEGDIO1, if LCD_MAP[1] = 0. Causes WPULSE to be output on pin SEGDIO0, if LCD_MAP[0] = 0. Causes XPULSE to be output on pin SEGDIO6 , if LCD_MAP[6] = 0. Causes YPULSE to be output on pin SEGDIO7 , if LCD_MAP[7] = 0. Serial EEPROM interface data.
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71M6541D/F/G and 71M6542F/G Data Sheet Name EX_XFER EX_RTC1S EX_RTC1M EX_RTCT EX_SPI EX_EEX EX_XPULSE EX_YPULSE EX_WPULSE EX_VPULSE Location 2700[0] 2700[1] 2700[2] 2700[3] 2701[7] 2700[7] 2700[6] 2700[5] 2701[6] 2701[5] Rst Wk Dir 0 0 Interrupt enable bits. These bits enable the XFER_BUSY, the RTC_1SEC, etc. The bits are set by hardware and cannot be set by writing a 1. The bits R/W are reset by writing 0.
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71M6541D/F/G and 71M6542F/G Data Sheet Name FL_BANK Location Rst Wk Dir SFR B6 01 01 R/W Description Flash Bank Selection (71M6541G and 71M6542G only) The program memory of the 71M6541G/71M6542G consists of a fixed lower bank of 32 KB, addressable at 0x0000 to 0x7FFF plus an upper banked area of 32 KB, addressable at 0x8000 to 0xFFFF. The I/O RAM register FL_BANK is used to switch one of four memory banks of 32 KB each into the address range from 0x8000 to 0xFFFF.
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71M6541D/F/G and 71M6542F/G Data Sheet Name Location FLSH_PSTWR SFR B2[2] 0 0 FLSH_PWE SFR B2[0] 0 0 FLSH_RDE 2702[2] – – FLSH_UNLOCK[3:0] 2702[7:4] 0 0 FLSH_WRE IE_XFER IE_RTC1S IE_RTC1M IE_RTCT IE_SPI IE_EEX IE_XPULSE IE_YPULSE IE_WPULSE IE_VPULSE 2702[1] SFR E8[0] SFR E8[1] SFR E8[2] SFR E8[4] SFR F8[7] SFR E8[7] SFR E8[6] SFR E8[5] SFR F8[6] SFR F8[5] – – 0 0 INTBITS 2707[6:0] – – LCD_ALLCOM 2400[3] 0 – LCD_BAT 2402[7] 0 – 2401[5:0] 2402[5:0] 0 – LCD_BLNKMAP23[5:0]
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71M6541D/F/G and 71M6542F/G Data Sheet Name Location Rst Wk Dir Description Sets the LCD clock frequency.
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71M6541D/F/G and 71M6542F/G Data Sheet Name LCD_SEG0[5:0] to LCD_SEG15[5:0] LCD_SEGDIO16[5:0] to LCD_SEGDIO45[5:0] LCD_SEG46[5:0] to LCD_SEG50[5:0] LCD_SEGDIO51[5:0] to LCD_SEGDIO55[5:0] LCD_VMODE[1:0] LCD_Y LKPADDR[6:0] LKPAUTOI LKPDAT[7:0] LKP_RD LKP_WR 118 Location Rst Wk Dir Description 2410[5:0] to 241F[5:0] 0 – R/W 2420[5:0] to 243D[5:0] 0 – SEG and DIO data for SEGDIO16 through SEGDIO45.
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71M6541D/F/G and 71M6542F/G Data Sheet Name Location MPU_DIV[2:0] 2200[2:0] 0 0 R/W MUX0_SEL[3:0] MUX1_SEL[3:0] MUX2_SEL[3:0] MUX3_SEL[3:0] MUX4_SEL[3:0] MUX5_SEL[3:0] MUX6_SEL[3:0] MUX7_SEL[3:0] MUX8_SEL[3:0] MUX9_SEL[3:0] MUX10_SEL[3:0] 2105[3:0] 2105[7:4] 2104[3:0] 2104[7:4] 2103[3:0] 2103[7:4] 2102[3:0] 2102[7:4] 2101[3:0] 2101[7:4] 2100[3:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MUX_DIV[3:0] 2100[7:4] 0 0 R/W 2457[0] 0 – R/W OPT_BB
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71M6541D/F/G and 71M6542F/G Data Sheet Name OPT_RXINV OPT_TXE [1:0] Location 2457[1] 2456[3:2] Rst Wk Dir 0 – R/W 00 – R/W OPT_TXINV 2456[0] 0 – R/W OPT_TXMOD 2456[1] 0 – R/W OSC_COMP 28A0[5] 0 – R/W PB_STATE SFR F8[0] 0 0 R PERR_RD PERR_WR SFR FC[6] SFR FC[5] 0 0 R/W PLL_OK SFR F9[4] 0 0 R 2200[4] 0 0 R/W PLL_FAST PLS_MAXWIDTH[7:0] 120 210A[7:0] FF FF R/W Description Inverts result from OPT_RX comparator when 1. Affects only the UART input.
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71M6541D/F/G and 71M6542F/G Data Sheet Name Location PLS_INTERVAL[7:0] 210B[7:0] Rst Wk Dir Description PLS_INTERVAL[7:0] determines the interval time between pulses. The time between output pulses is PLS_INTERVAL[7:0]*4 in units of CK_FIR clock cycles. If PLS_INTERVAL[7:0] = 0, the FIFO is not used and pulses are output as soon as the CE issues them.
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71M6541D/F/G and 71M6542F/G Data Sheet Name Location RTC_P[16:14] RTC_P[13:6] RTC_P[5:0] 289B[2:0] 289C[7:0] 289D[7:2] 4 0 0 4 0 0 R/W RTC_Q[1:0] 289D[1:0] 0 0 R/W 2890[6] 0 0 R/W RTC_SBSC[7:0] RTC_TMIN[5:0] 2892[7:0] 289E[5:0] – 0 – – R R/W RTC_THR[4:0] 289F[4:0] 0 – R/W 2890[7] 0 0 R/W RTC_SEC[5:0] RTC_MIN[5:0] RTC_HR[4:0] RTC_DAY[2:0] RTC_DATE[4:0] RTC_MO[3:0] RTC_YR[7:0] 2893[5:0] 2894[5:0] 2895[4:0] 2896[2:0] 2897[4:0] 2898[3:0] 2899[7:0] – – – – – – – – – – – – – – R/
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71M6541D/F/G and 71M6542F/G Data Sheet Name Location SECURE SFR B2[6] 0 0 28B2[7] 0 0 SFR FD[7:0] – – SPI_E 270C[4] 1 1 SPI_SAFE 270C[3] 0 0 SPI_STAT[7:0] 2708[7:0] 0 0 STEMP[10:3] STEMP[2:0] SUM_SAMPS[12:8] SUM_SAMPS[7:0] 2881[7:0] 2882[7:5] 2107[4:0] 2108[7:0] – – – – 0 0 28A0[3] 0 0 230A[2:0] 230B[7:0] 0 – R TEMP_BAT 28A0[4] 0 – R/W TEMP_BSEL 28A0[7] 0 – SLEEP SPI_CMD[7:0] TBYTE_BUSY TEMP_22[10:8] TEMP_22[7:0] Rev 4 Rst Wk Dir Description Inhibits erasure
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71M6541D/F/G and 71M6542F/G Data Sheet Name TBYTE_BUSY TEMP_PER[2:0] Location Rst Wk Dir 28A0[3] 0 0 R 28A0[2:0] 0 – R/W TEMP_PWR 28A0[6] TEMP_START 28B4[6] TMUX[5:0] TMUX2[4:0] TMUXRA[2:0] 2502[5:0] 2503[4:0] 270A[2:0] VERSION[7:0] TEMP_PER 0 1-6 7 Time (seconds) No temperature updates 2(3+TEMP_PER) Continuous updates Selects the power source for the temp sensor: R/W 1 = V3P3D, 0 = VBAT_RTC. This bit is ignored in SLP and LCD modes, where the temp sensor is always powered by VBAT_RTC.
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71M6541D/F/G and 71M6542F/G Data Sheet Name Location Rst Wk Dir VSTAT[2:0] SFR F9[2:0] – – WAKE_ARM 28B2[5] 0 – 2880[7:0] 0 – WD_RST 28B4[7] 0 0 WF_DIO4 28B1[2] 0 – WF_DIO52 28B1[1] 0 – WF_DIO55 28B1[0] 0 – WF_TMR WF_PB WF_RX WF_CSTART WF_RST WF_RSTBIT WF_OVF WF_ERST WF_BADVDD 28B1[5] 28B1[3] 28B1[4] 28B0[7] 28B0[6] 28B0[5] 28B0[4] 28B0[3] 28B0[2] 0 0 0 0 1 0 0 0 0 – – – WAKE_TMR[7:0] Rev 4 – Description This word describes the source of power and the status of the VDD.
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71M6541D/F/G and 71M6542F/G Data Sheet 5.3 CE Interface Description 5.3.1 CE Program The CE performs the precision computations necessary to accurately measure energy. These computations include offset cancellation, phase compensation, product smoothing, product summation, frequency detection, VAR calculation, sag detection and voltage phase measurement. All data computed by the CE is dependent on the selected meter equation as given by EQU[2:0] (I/O RAM 0x2106[7:5]).
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71M6541D/F/G and 71M6542F/G Data Sheet The parameters EQU[2:0] (I/O RAM 0x2106[7:5]), CE_E (I/O RAM 0x2106[0]), and SUM_SAMPS[12:0] are essential to the function of the CE are stored in I/O RAM (see 5.2 I/O RAM Map – Alphabetical Order for details). 5.3.
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71M6541D/F/G and 71M6542F/G Data Sheet 5.3.6 CE Front End Data (Raw Data) Access to the raw data provided by the AFE is possible by reading addresses 0-3, 9 and 10 (decimal) shown in Table 79. The MUX_SEL column in Table 79 shows the MUX_SEL handles for the various sensor input pins. For example, if differential mode is enable via control bit DIFFA_E = 1 (I/O RAM 0x210C[4]), then the inputs IAP and IAN are combined together to form a single differential input and the corresponding MUX_SEL handle is 0.
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71M6541D/F/G and 71M6542F/G Data Sheet status flags for the preceding CE code pass (CE_BUSY interrupt). The significance of the bits in CESTATUS is shown in Table 81. Table 81: CESTATUS (CE RAM 0x80) Bit Definitions CESTATUS bit 31:4 3 2 Not Used F0 Not Used 1 SAG_B 0 SAG_A Name Description These unused bits are always zero. F0 is a square wave at the exact fundamental input frequency. This unused bit is always zero. Normally zero. Becomes one when VB remains below SAG_THR for SAG_CNT samples.
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71M6541D/F/G and 71M6542F/G Data Sheet 5 EXT_PULSE 1 4:2 Reserved 0 1 PULSE_FAST 0 0 PULSE_SLOW 0 When zero, causes the pulse generators to respond to internal data (WPULSE = WSUM_X (CE RAM 0x84), VPULSE = VARSUM_X (CE RAM 0x88)). Otherwise, the generators respond to values the MPU places in APULSEW and APULSER (CE RAM 0x45 and 0x49). Reserved. When PULSE_FAST = 1, the pulse generator input is increased 16x. When PULSE_SLOW = 1, the pulse generator input is reduced by a factor of 64.
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71M6541D/F/G and 71M6542F/G Data Sheet 5.3.8 CE Transfer Variables When the MPU receives the XFER_BUSY interrupt, it knows that fresh data is available in the transfer variables. CE transfer variables are modified during the CE code pass that ends with an XFER_BUSY interrupt. They remain constant throughout each accumulation interval. In this data sheet, the names of CE transfer variables always end with “_X”.
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71M6541D/F/G and 71M6542F/G Data Sheet WSUM_X (CE RAM 0x84) and VARSUM_X (CE RAM 0x88) are the signed sum of Phase-A and Phase-B Wh or VARh values according to the metering equation specified in the I/O RAM control field EQU[2:0] (I/O RAM 0x2106[7:5]). WxSUM_X (x = 0 or 1, CE RAM 0x85 and 0x86) is the Wh value accumulated for phase x in the last accumulation interval and can be computed based on the specified LSB value. 5.3.8.
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71M6541D/F/G and 71M6542F/G Data Sheet Table 89: Other Transfer Variables CE Address Name Description 2520.6 Hz ≈ 0.509 ⋅ 10− 6 Hz(for Local) 232 2520.6 Hz ≈ 0.587 ⋅ 10− 6 Hz(for Remote) LSB ≡ 232 The number of edge crossings of the selected voltage in the previous accumulation interval. Edge crossings are either direction and are de-bounced. Fundamental frequency: LSB ≡ 0x82 FREQ_X 0x83 MAINEDGE_X 5.3.9 Pulse Generation Table 90 describes the CE pulse generation parameters.
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71M6541D/F/G and 71M6542F/G Data Sheet Table 90: CE Pulse Generation Parameters CE Address Name Default Description Kh = 0x21 WRATE 547 0x22 0x23 KVAR SUM_SAMPS 6444 2520 0x45 APULSEW 0 0x46 WPULSE_CTR 0 0x47 WPULSE_FRAC 0 0x48 0x49 0x4A WSUM_ACCUM APULSER VPULSE_CTR 0 0 0 0x4B VPULSE_FRAC 0 0x4C VSUM_ACCUM 0 134 VMAX ⋅ IMAX ⋅ K ⋅ Wh / pulse WRATE ⋅ N ACC ⋅ X where: K = 66.1782 (Local Sensors) K = 109.1587 (Remote Sensor) K = 47.
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71M6541D/F/G and 71M6542F/G Data Sheet 5.3.10 Other CE Parameters Table 91 shows the CE parameters used for suppression of noise due to scaling and truncation effects. Table 91: CE Parameters for Noise Suppression and Code Version CE Name Default Description Address QUANT_VA 0x25 0 QUANT_IA 0x26 0 Compensation factors for truncation and noise in voltage, current, real energy and reactive energy for phase A.
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71M6541D/F/G and 71M6542F/G Data Sheet 5.3.11 CE Calibration Parameters Table 92 lists the parameters that are typically entered to effect calibration of meter accuracy. Table 92: CE Calibration Parameters CE Address 0x10 0x11 0x13 0x14† Name Default CAL_IA CAL_VA CAL_IB CAL_VB 16384 16384 16384 16384 0x12 PHADJ_A 0 Description These constants control the gain of their respective channels. The nominal value for each parameter is 214 = 16384.
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71M6541D/F/G and 71M6542F/G Data Sheet 5.3.12 CE Flow Diagrams Figure 44 through Figure 46 show the data flow through the CE in simplified form. Functions not shown include delay compensation, sag detection, scaling and the processing of meter equations.
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71M6541D/F/G and 71M6542F/G Data Sheet SUM Σ W0 W1 Σ VAR0 Σ VAR1 Σ W0SUM_X MPU W1SUM_X VAR0SUM_X VAR1SUM_X SUM_SAMPS=2520 SQUARE I0 SUM I0SQ I2 V0SQ V0 V2 I1 I2 I1SQ Σ I0SQSUM_X Σ V0SQSUM_X Σ I1SQSUM_X F0 Figure 46: CE Data Flow: Squaring and Summation Stages 138 Rev 4
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71M6541D/F/G and 71M6542F/G Data Sheet 6 Electrical Specifications This section provides the electrical specifications for the 71M654x. Please refer to the 71M6xxx Data Sheet for the 71M6x01 electrical specifications, pin-out, and package mechanical data. The devices are 100% production tested at room temperature, and performance over the full temperature range is guaranteed by design. 6.1 Absolute Maximum Ratings Table 93 shows the absolute maximum ratings for the device.
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71M6541D/F/G and 71M6542F/G Data Sheet Temperature and ESD Stress Operating junction temperature (peak, 100ms) Operating junction temperature (continuous) Storage temperature Solder temperature – 10 second duration ESD stress on all pins 6.
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71M6541D/F/G and 71M6542F/G Data Sheet 6.4 Performance Specifications 6.4.1 Input Logic Levels Table 96: Input Logic Levels Parameter Digital high-level input voltage1, VIH Digital low-level input voltage1, VIL Input pullup current, IIL E_RXTX, E_RST, E_TCLK OPT_RX, OPT_TX SPI_CSZ (SEGDIO36) Other digital inputs Input pull down current, IIH ICE_E, RESET, TEST Other digital inputs Condition VIN=0 V, ICE_E=3.3 V Min 2 Typ Max 0.
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71M6541D/F/G and 71M6542F/G Data Sheet 6.4.3 Battery Monitor Table 98: Battery Monitor Performance Specifications (TEMP_BAT= 1) Parameter BV: Battery Voltage (definition) Measurement Error  BV  100 ⋅  − 1  VBAT  Input impedance in continuous measurement, MSN mode. V(VBAT_RTC)/I(VBAT_RTC) Load applied with BCURR IBAT(BCURR=1) - IBAT(BCURR=0) 6.4.4 Condition Min Typ Max Unit 𝐵𝑉 = 3.3𝑉 + (𝐵𝑆𝐸𝑁𝑆𝐸 − 142) ∙ 0.0246𝑉 + 𝑆𝑇𝐸𝑀𝑃 ∙ 297𝜇𝑉 MSN mode, TEMP_PWR = 1 V 𝐵𝑉 = 3.291𝑉 + (𝐵𝑆𝐸𝑁𝑆𝐸 − 142) ∙ 0.
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71M6541D/F/G and 71M6542F/G Data Sheet 6.4.5 Supply Current The supply currents provided in Table 100 below include only the current consumed by the 71M654x. Refer to the 71M6xxx Data Sheet for additional current required when using a 71M6x01 remote sensor. Table 100: Supply Current Performance Specifications Parameter Condition I1: V3P3A + V3P3SYS current, Half-Speed (ADC_DIV=1) (see note 1) Single-phase: 2 Currents, 1 Voltage V3P3A = V3P3SYS = 3.
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71M6541D/F/G and 71M6542F/G Data Sheet 6.4.6 V3P3D Switch Table 101: V3P3D Switch Performance Specifications Parameter On resistance – V3P3SYS to V3P3D On resistance – VBAT to V3P3D V3P3D IOH, MSN V3P3D IOH, BRN 6.4.7 Condition | IV3P3D | ≤ 1 mA | IV3P3D | ≤ 1 mA, VBAT>2.5V V3P3SYS = 3V V3P3D = 2.9V VBAT = 2.6V V3P3D = 2.5V Min Typ Max 10 Unit Ω 10 Ω 10 mA 10 mA Internal Power Fault Comparators Table 102.
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71M6541D/F/G and 71M6542F/G Data Sheet 6.4.9 2.5 V Voltage Regulator – Battery Power Unless otherwise specified, V3P3SYS = V3P3A = 0, PB=GND (BRN). Table 104: Low-Power Voltage Regulator Performance Specifications Parameter Condition VBAT = 3.0 V - 3.8 V, V3P3 = 0 V, ILOAD = 0 mA VBAT = 3.3 V, V3P3 = 0 V, ILOAD = 0 mA to 1 mA ILOAD = 0ma, VBAT = 2.0 V, V3P3 = 0 V. V2P5 V2P5 load regulation Voltage Overhead 2V − VBAT-VDD Min Typ Max Unit 2.55 2.65 2.75 V 40 mV 200 mV 6.4.
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71M6541D/F/G and 71M6542F/G Data Sheet 6.4.12 LCD Drivers Table 107: LCD Driver Performance Specifications Parameter VLCD Current (see Notes 1 to 4) Notes: 1. 2. 3. 4. 146 Condition Min Typ VLCD=3.3, all LCD map bits=0 VLCD=5.0, all LCD map bits=0 Max 2 3 Unit uA uA These specifications apply to all COM and SEG pins. VLCD = 2.5 V to 5 V. LCD_VMODE=3, LCD_ON=1, LCD_BLANK=0, LCD_MODE=6, LCD_CLK=2. Output load is 74 pF per SEG and COM pin.
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71M6541D/F/G and 71M6542F/G Data Sheet 6.4.13 VLCD Generator Table 108: LCD Driver Performance Specifications1 Parameter VSYS to VLCD switch impedance VBAT to VLCD switch impedance LCD Boost Frequency VLCD IOH current (VLCD(0)-VLCD(IOH)<0.25) Condition V3P3 = 3.3 V, RVLCD=removed, LCD_BAT=0, LCD_VMODE[1:0]=0, ∆ILCD=10 µA V3P3 = 0 V, VBAT = 2.
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71M6541D/F/G and 71M6542F/G Data Sheet Parameter Condition Min Typ Max Unit LCD_DAC Error. VLCD-VLCDnom LCD_VMODE[1:0] = 1, LCD_DAC[4:0] = C, DAC=12, no Boost LCD_CLK[1:0]=2, -0.5 V V3P3 = 3.6 V LCD_MODE[2:0]=6 -1.1 V V3P3 = 3.0 V 2 2 -0.15 0.15 V VBAT = 4.0 V, V3P3 = 0 V, BRN Mode -1.52 V VBAT = 2.5 V, V3P3 = 0 V, BRN Mode LCD_DAC Error. VLCD-VLCDnom LCD_VMODE[1:0] = 1, LCD_DAC[4:0] = 0, Zero Scale, no Boost LCD_CLK[1:0]=2, -0.15 0.15 V V3P3 = 3.6 V LCD_MODE[2:0]=6 -0.15 0.15 V V3P3 = 3.0 V -0.15 0.
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71M6541D/F/G and 71M6542F/G Data Sheet 6.4.14 VREF Table 109 shows the performance specifications for the ADC reference voltage (VREF). Table 109: VREF Performance Specifications Parameter VREF output voltage, VREF(22) VREF output voltage, VREF(22) Condition TA = 22 ºC VREF power supply sensitivity ΔVREF / ΔV3P3A V3P3A = 3.0 to 3.6 V VNOM definition (see note 2) VNOM temperature coefficients: TC1 = TC2 = Max Unit 1.193 1.195 1.197 V 1.
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71M6541D/F/G and 71M6542F/G Data Sheet 6.4.15 ADC Converter Table 110. ADC Converter Performance Specifications Parameter Condition Recommended Input Range (Vin - V3P3A) Voltage to Current Crosstalk 6 10 *Vcrosstalk cos(∠Vin − ∠Vcrosstalk ) Vin (see note 1) Input Impedance, no pre-amp ADC Gain Error vs %Power Supply Variation 10 6 ∆Nout PK 357nV / VIN 100 ∆V 3P3 A / 3.
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71M6541D/F/G and 71M6542F/G Data Sheet Notes: 1. Guaranteed by design; not production tested. 2. Unless stated otherwise, the following test conditions apply to all the parameters provided in this table: FIR_LEN[1:0]=1, VREF_DIS=0, PLL_FAST=1, ADC_DIV=0, MUX_DIV=6, LSB values do not include the 9-bit left shift at CE input. 6.4.
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71M6541D/F/G and 71M6542F/G Data Sheet 6.5 Timing Specifications 6.5.1 Flash Memory Table 112: Flash Memory Timing Specifications Parameter Condition Flash write cycles Flash data retention -40 °C to +85 °C 25 °C 85 °C Min Typ Max 20,000 100 10 Cycles Years Flash byte writes between page or mass erase operations Write Time per Byte Page Erase (1024 bytes) Mass Erase 6.5.2 Unit 2 Cycles 21 21 21 µs ms Ms SPI Slave Table 113.
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71M6541D/F/G and 71M6542F/G Data Sheet 6.5.4 RESET Pin Table 115: RESET Pin Timing Parameter Condition Reset pulse width Reset pulse fall time (see note 1) Notes: 1. Guaranteed by design; not production tested. 6.5.
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71M6541D/F/G and 71M6542F/G Data Sheet 6.6 Package Outline Drawings 6.6.1 64-Pin LQFP Outline Package Drawing 11.7 12.3 11.7 + 12.3 PIN No. 1 Indicator 9.8 10.2 0.50 Typ. 0.60 Typ. 0.00 0.20 0.14 0.28 1.40 1.
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71M6541D/F/G and 71M6542F/G Data Sheet 6.6.2 100-Pin LQFP Package Outline Drawing Controlling dimensions are in mm. 15.7(0.618) 16.3(0.641) 1 15.7(0.618) 16.3(0.641) Top View 14.000 +/- 0.200 MAX. 1.600 1.50 +/- 0.10 0.225 +/- 0.045 0.50 TYP. 0.10 +/- 0.10 0.
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71M6541D/F/G and 71M6542F/G Data Sheet Package Markings 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 71M6541DIGT.
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71M6541D/F/G and 71M6542F/G Data Sheet Pinout Diagrams 6.8.1 71M6541D/F/G LQFP-64 Package Pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 SPI_CKI/SEGDIO39 SEGDIO44 SEGDIO45 TMUX2OUT/SEG46 TMUXOUT/SEG47 RESET PB VLCD VREF IAP IAN V3P3A VA TEST GNDA XOUT 6.
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71M6541D/F/G and 71M6542F/G Data Sheet 71M6542F/G LQFP-100 Package Pinout 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 SPI_CKI/SEGDIO39 SEGDIO40 SEGDIO41 SEGDIO42 SEGDIO43 SEGDIO44 SEGDIO45 TMUX2OUT/SEG46 TMUXOUT/SEG47 RESET PB VLCD VREF IAP IAN V3P3A NC VB VA TEST GNDA NC NC NC XOUT 6.8.
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71M6541D/F/G and 71M6542F/G Data Sheet 6.9 Pin Descriptions 6.9.1 Power and Ground Pins Pin types: P = Power, O = Output, I = Input, I/O = Input/Output. The circuit number denotes the equivalent circuit, as specified under 6.9.4 I/O Equivalent Circuits. .
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71M6541D/F/G and 71M6542F/G Data Sheet 6.9.2 Analog Pins Table 120: Analog Pins † Pin Pin (64 pin) (100-pin) Name 55 54 87 86 IAPIAN 44 43 68 67 IBPIBN 52 -- 82 83 56 48 49 Type Circuit I 6 VA VB† I 6 88 VREF O 9 75 76 XIN XOUT I O 8 Description Differential or single-ended Line Current Sense Inputs: These pins are voltage inputs to the internal A/D converter. Typically, they are connected to the outputs of current sensors. Unused pins must be tied to V3P3A.
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71M6541D/F/G and 71M6542F/G Data Sheet 6.9.3 Digital Pins Table 121 lists the digital pins. Pin types: P = Power, O = Output, I = Input, I/O = Input/Output, N/C = no connect. The circuit number denotes the equivalent circuit, as specified in 6.9.4 I/O Equivalent Circuits.
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71M6541D/F/G and 71M6542F/G Data Sheet Pin (64-pin) Pin (100-pin) Name 39 59 ICE_E 60 92 TMUXOUT/SEG47 61 93 TMUX2OUT/SEG46 Type Circuit I 2 ICE Enable. When zero, E_RST, E_TCLK, and E_RXTX become SEG50, SEG49, and SEG48 respectively. For production units, this pin should be pulled to GND to disable the emulator port. O 4, 5 Multiple-Use Pins. Configurable as either multiplexer/clock output or LCD segment driver using the I/O RAM registers.
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71M6541D/F/G and 71M6542F/G Data Sheet 6.9.
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71M6541D/F/G and 71M6542F/G Data Sheet 7 Ordering Information 7.1 71M6541D/F/G and 71M6542F/G Table 122. Ordering Information Part Part Description (Package, Typical Accuracy) 71M6541D 64-pin LQFP Lead-Free, 0.1% 71M6541D 64-pin LQFP Lead-Free, 0.1% 71M6541F 64-pin LQFP Lead-Free, 0.1% 71M6541F 64-pin LQFP Lead-Free, 0.1% 71M6541G 71M6542F 64-pin LQFP Lead-Free, 0.1% 100-pin LQFP Lead-Free, 0.1% 71M6542F 100-pin LQFP Lead-Free, 0.1% 71M6542G 100-pin LQFP Lead-Free, 0.
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71M6541D/F/G and 71M6542F/G Data Sheet Appendix A: Acronyms AFE AMR ANSI CE DIO DSP FIR I2C ICE IEC MPU PLL RMS SFR SOC SPI TOU UART Rev 4 Analog Front End Automatic Meter Reading American National Standards Institute Compute Engine Digital I /O Digital Signal Processor Finite Impulse Response Inter-IC Bus In-Circuit Emulator International Electrotechnical Commission Microprocessor Unit (CPU) Phase-locked loop Root Mean Square Special Function Register System on Chip Serial Peripheral Interface Time of U
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71M6541D/F/G and 71M6542F/G Data Sheet Appendix B: Revision History REVISION NUMBER 1.0 REVISION DATE 3/11 1.1 4/11 2 11/11 DESCRIPTION Initial release Removed the information about 18mW typ consumption at 3.3V in sleep mode from the Features section Updated the Temperature Measurement Equation and Temperature Error parameters in Table 99 Promoted 71M6542G to production level (Table 122) Added references to 71M6541G/2G throughout the document, as appropriate.