Datasheet

71M6541D/F/G and 71M6542F/G Data Sheet
116 Rev 4
Name Location
Rst
Wk Dir Description
FLSH_PSTWR
SFR B2[2] 0 0 R/W
Enables timed flash writes. When 1, and if
CE_E
= 1, flash write requests are
stored in a one-element deep FIFO and are executed when CE_BUSY falls.
FLSH_PEND can be read to determine the status of the FIFO. If
FLSH_PSTWR = 0 or if CE_E = 0, flash writes are immediate.
FLSH_PWE
SFR B2[0] 0 0 R/W
Program Write Enable
0 = MOVX commands refer to External RAM Space, normal operation (default).
1 = MOVX @DPTR,A moves A to External Program Space (Flash) @ DPTR.
This bit is automatically reset after each byte written to flash. Writes to this bit
are inhibited when interrupts are enabled.
FLSH_RDE
2702[2] – – R
Indicates that the flash may be read by ICE or SPI slave. FLSH_RDE =
(!SECURE)
FLSH_UNLOCK[3:0]
2702[7:4] 0 0 R/W
Must be a ‘2’ to enable any flash modification. See the description of Flash
security for more details.
FLSH_WRE
2702[1]
–
–
R
Indicates that the flash may be written through ICE or SPI slave ports.
IE_XFER
IE_RTC1S
IE_RTC1M
IE_RTCT
IE_SPI
IE_EEX
IE_XPULSE
IE_YPULSE
IE_WPULSE
IE_VPULSE
SFR E8[0]
SFR E8[1]
SFR E8[2]
SFR E8[4]
SFR F8[7]
SFR E8[7]
SFR E8[6]
SFR E8[5]
SFR F8[6]
SFR F8[5]
0 0 R/W
Interrupt flags for external interrupts 2 and 6. These flags monitor the source
of the int6 and int2 interrupts (external interrupts to the MPU core). These
flags are set by hardware and must be cleared by the software interrupt
handler. The IEX2 (SFR 0xC0[1]) and IEX6 (SFR 0xC0[5]) interrupt flags are
automatically cleared by the MPU core when it vectors to the interrupt
handler. IEX2 and IEX6
must be cleared by writing zero to their corresponding
bit positions in SFR 0xC0, while writing ones to the other bit positions that are
not being cleared.
INTBITS
2707[6:0] – – R
Interrupt inputs. The MPU may read these bits to see the input to external
interrupts INT0, INT1, up to INT6. These bits do not have any memory and
are primarily intended for debug use.
LCD_ALLCOM
2400[3] 0 – R/W
Configures SEG/COM bits as COM. Has no effect on pins whose LCD_MAP
bit is zero.
LCD_BAT
2402[7]
0
–
R/W
Connects the LCD power supply to VBAT in all modes.
LCD_BLNKMAP23[5:0]
LCD_BLNKMAP22[5:0]
2401[5:0]
2402[5:0]
0 – R/W
Identifies which segments connected to SEG23 and SEG22 should blink. 1
means ‘blink.’ The most significant bit corresponds to COM5, the least
significant, to COM0.