Datasheet
71M6541D/F/G and 71M6542F/G Data Sheet
Rev 4 117
Name Location
Rst
Wk
Dir Description
LCD_CLK[1:0]
2400[1:0] 0 – R/W
Sets the LCD clock frequency. Note: f
w
= 32768 Hz
LCD_CLK
LCD Clock Frequency
LCD_CLK
LCD Clock Frequency
00
9
2
W
f
= 64 Hz
10
7
2
W
f
= 256 Hz
01
8
2
W
f
= 128 Hz
11
6
2
W
f
= 512 Hz
LCD_DAC[4:0]
240D[4:0] 0 – R/W
The LCD contrast DAC. This DAC controls the VLCD voltage and has an
output range of 2.5 V to 5 V. The VLCD voltage is
VLCD = 2.5 + 2.5 * LCD_DAC[4:0]/31
Thus, the LSB of the DAC is 80.6 mV. The maximum DAC output voltage is
limited by V3P3SYS, VBAT, and whether LCD_BSTE = 1.
LCD_E
2400[7] 0 – R/W
Enables the LCD display. When disabled, VLC2, VLC1, and VLC0 are
ground as are the COM and SEG outputs if their LCD_MAP bit is 1.
LCD_MAP[55:48]
LCD_MAP[47:40]
LCD_MAP[39:32]
LCD_MAP[31:24]
LCD_MAP[23:16]
LCD_MAP[15:8]
LCD_MAP[7:0]
2405[7:0]
2406[7:0]
2407[7:0]
2408[7:0]
2409[7:0]
240A[7:0]
240B[7:0]
0
0
0
0
0
0
0
–
–
–
–
–
–
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Enables LCD segment driver mode of combined SEGDIO pins. Pins that
cannot be configured as outputs (SEG48 through SEG50) become inputs with
internal pull ups when their LCD_MAP bit is zero. Also, note that SEG48
through SEG50 are multiplexed with the in-circuit emulator signals. When the
ICE_E pin is high, the ICE interface is enabled, and SEG48 through SEG50
become E_RXTX, E_TCLK and E_RST, respectively.
LCD_MODE[2:0]
2400[6:4] 0 – R/W
Selects the LCD bias and multiplex mode.
LCD_MODE
Output
LCD_MODE
Output
000
4 states, 1/3 bias
100
Static display
001
3 states, 1/3 bias
101
5 states, 1/3 bias
010
2 states, ½ bias
110
6 states, 1/3 bias
011
3 states, ½ bias
LCD_ON
LCD_BLANK
240C[0]
240C[1]
0
0
–
–
R/W
R/W
Turns on or off all LCD segments without changing LCD data. If both bits are
set, the LCD display is turned on.
LCD_ONLY
28B2[6] 0 0 W
Puts the IC
to sleep, but with LCD display still active. Ignored if system power
is present. It awakens when Wake Timer times out, when certain DIO pins
are raised, or when system power returns. See 3.2 Battery Modes.
LCD_RST
240C[2] 0 – R/W
Clear all bits of LCD data. These bits affect SEGDIO pins that are configured
as LCD drivers. This bit does not auto clear.