Datasheet

71M6541D/F/G and 71M6542F/G Data Sheet
Rev 4 119
Name Location
Rst
Wk Dir Description
MPU_DIV[2:0]
2200[2:0] 0 0 R/W
MPU clock rate is:
MPU Rate = MCK Rate * 2
-(2+
MPU_DIV
[2:0])
.
The maximum value for MPU_DIV[2:0] is 4. Based on the default values of
the PLL_FAST bit and MPU_DIV[2:0], the power up MPU rate is 6.29 MHz
/ 4
= 1.5725 MHz. The minimum MPU clock rate is 38.4 kHz when PLL_FAS T =
1.
MUX0_SEL[3:0]
2105[3:0]
0
0
R/W
Selects which ADC input is to be converted during time slot 0.
MUX1_SEL[3:0]
2105[7:4]
0
0
R/W
Selects which ADC input is to be converted during time slot 1.
MUX2_SEL[3:0]
2104[3:0]
0
0
R/W
Selects which ADC input is to be converted during time slot 2.
MUX3_SEL[3:0]
2104[7:4]
0
0
R/W
Selects which ADC input is to be converted during time slot 3.
MUX4_SEL[3:0]
2103[3:0]
0
0
R/W
Selects which ADC input is to be converted during time slot 4.
MUX5_SEL[3:0]
2103[7:4]
0
0
R/W
Selects which ADC input is to be converted during time slot 5.
MUX6_SEL[3:0]
2102[3:0]
0
0
R/W
Selects which ADC input is to be converted during time slot 6.
MUX7_SEL[3:0]
2102[7:4]
0
0
R/W
Selects which ADC input is to be converted during time slot 7.
MUX8_SEL[3:0]
2101[3:0]
0
0
R/W
Selects which ADC input is to be converted during time slot 8.
MUX9_SEL[3:0]
2101[7:4]
0
0
R/W
Selects which ADC input is to be converted during time slot 9.
MUX10_SEL[3:0]
2100[3:0]
0
0
R/W
Selects which ADC input is to be converted during time slot 10.
MUX_DIV[3:0]
2100[7:4] 0 0 R/W
MUX_DIV[3:0] is the number of ADC time slots in each MUX frame. The
maximum number of time slots is 11.
OPT_BB
2457[0] 0 – R/W
Configures the input of the optical port to be a DIO pin to allow it to be
bit-banged. In this case, DIO5 becomes a third high speed UART. Refer to
2.5.7 UART and Optical Interface under the “Bit Banged Optical UART
(Third UART)” sub-heading on page 58.
OPT_FDC[1:0]
2457[5:4] 0 – R/W
Selects OPT_TX modulation duty cycle.
OPT_FDC
Function
00
50% Low
01
25% Low
10
12.5% Low
11
6.25% Low
OPT_RXDIS
2457[2] 0 – R/W
OPT_RX can be configured as an input to the optical UART or as SEGDIO55.
OPT_RXDIS = 0 and LCD_MAP[55] = 0: OPT_RX
OPT_RXDIS = 1 and LCD_MAP[55] = 0: DIO55
OPT_RXDIS = 0 and LCD_MAP[55] = 1: SEG55
OPT_RXDIS = 1 and LCD_MAP[55] = 1: SEG55