Datasheet

71M6541D/F/G and 71M6542F/G Data Sheet
24 Rev 4
Name Address
RST
Default
WAKE
Default
R/W Description
itself is in RCMD[4:2].
PERR_RD
PERR_WR
SFR FC[6]
SFR FC[5]
0 0 R/W
The 71M654x sets these bits to indicate that a
parity error on the isolated sensor has been de-
tected. Once set, the bits are remembered until
they are cleared by the MPU.
CHOPR[1:0]
2709[7:6] 00 00 R/W
The CHOP settings for the isolated sensors.
00 – Auto chop. Change every multiplexer frame.
01 – Positive
10 – Negative
11 – Same as 00
TMUXRB[2:0]
270A[2:0]
000
000
R/W
The TMUX bits for control of the isolated sensor.
RMT_RD[15:8]
RMT_RD[7:0]
2602[7:0]
2603[7:0]
0 0 R The read buffer for 71M6x01 read operations.
RFLY_DIS
210C[3]
0 0 R/W
Controls how the 71M654x drives the 71M6x01
power pulse. When set, the power pulse is driven
high and low. When cleared, it is driven high
followed by an open circuit flyback interval.
RMT_E
2709[3] 0 0 R/W
Enables the isolated remote sensor interface and
re-configures pins IBP-IBN as a balanced pair
digital remote interface.
Refer to Table 76 starting on page 111 for more complete details about these I/O RAM locations.
2.3 Digital Computation Engine (CE)
The CE, a dedicated 32-bit signal processor, performs the precision computations necessary to accurately
measure energy. The CE calculations and processes include:
• Multiplication of each current sample with its associated voltage sample to obtain the energy per
sample (when multiplied with the constant sample time).
• Frequency-insensitive delay cancellation on all four channels (to compensate for the delay between
samples caused by the multiplexing scheme).
• 90° phase shifter (for VAR calculations).
• Pulse generation.
• Monitoring of the input signal frequency (for frequency and phase information).
• Monitoring of the input signal amplitude (for sag detection).
• Scaling of the processed samples based on calibration coefficients.
• Scaling of samples based on temperature compensation information.
2.3.1 CE Program Memory
The CE program resides in flash memory. Common access to flash memory by the CE and MPU is controlled
by a memory share circuit. Each CE instruction word is two bytes long. Allocated flash space for the CE
program cannot exceed 4096 16-bit words (8 KB). The CE program counter begins a pass through the
CE code each time multiplexer state 0 begins. The code pass ends when a HALT instruction is executed.
For proper operation, the code pass must be completed before the multiplexer cycle ends.
The CE program must begin on a 1 KB boundary of the flash address. The I/O RAM control field
CE_LCTN[5:0] (I/O RAM 0x2109[5:0]) defines which 1 KB boundary contains the CE code. Thus, the first
CE instruction is located at 1024*CE_LCTN[5:0].
2.3.2 CE Data Memory
The CE and MPU share data memory (RAM). Common access to XRAM by the CE and MPU is controlled
by a memory share circuit. The CE can access up to 3 KB of the 3 KB data RAM (XRAM), i.e., from RAM
address 0x0000 to 0x0C00.