Datasheet

71M6541D/F/G and 71M6542F/G Data Sheet
26 Rev 4
equivalent to 203 ns) and contains a leading flag bit. See Figure 10 for the RTM output format. RTM is
low when not in use.
Figure 11 summarizes the timing relationships between the input MUX states, the CE_BUSY signal, and
the RTM serial output stream. In this example, MUX_DIV[3:0] = 4 (I/O RAM 0x2100[7:4]) and
FIR_LEN[1:0] = 10 (I/O RAM 0x210C[1]), (384), resulting in 4 ADC conversions. An ADC conversion
always consumes an integer number of CK32 clocks. Followed by the conversions is a single CK32
cycle.
Figure 11 also shows that the RTM serial data stream begins transmitting at the beginning of state S.
RTM, consisting of 140 CK cycles, always finishes before the next CE code pass starts.
Figure 10: RTM Timing
CK32
MUX STATE
0
MUX_DIV Conversions, MUX_DIV=4 is shown
Settle
ADC MUX Frame
ADC EXECUTION
S
MUX_SYNC
S
CE_EXECUTION
RTM
140
MAX CK COUNT
0 450
150
900 1350 1800
ADC0 ADC1 ADC2 ADC3
CK COUNT = CE_CYCLES + 1CK for each ADC transfer
NOTES:
1. ALL DIMENSIONS ARE 5MHZ CK COUNTS.
2. THE PRECISE FREQUENCY OF CK IS 150*CRYSTAL FREQUENCY = 4.9152MHz.
3. XFER_BUSY OCCURS ONCE EVERY SUM_SAMPS CODE PASSES.
CE_BUSY
XFER_BUSY
INITIATED BY A CE OPCODE AT END OF SUM INTERVAL
ADC TIMING
CE TIMING
RTM TIMING
1 2 3
Figure 11: Timing Relationship Between ADC MUX, CE, and RTM Serial Transfer
CKTEST
RTM
FLAG
RTM DATA0 (32 bits)
LSB
SIGN
LSB
SIGN
RTM DATA1 (32 bits)
LSB LSB
SIGN
SIGN
RTM DATA2 (32 bits)
RTM DATA3 (32 bits)
0 1 30 31 0 1 30 31 0 1 30 31 0 1 30 31
FLAG FLAG FLAG
MUX_STATE
S
MUX_SYNC
CK32