Datasheet

71M6541D/F/G and 71M6542F/G Data Sheet
Rev 4 67
Table 57 shows all I/O RAM registers that control the operation of the LCD interface.
Table 57: LCD Configurations
Name Location Rst Wk Dir Description
LCD_ALLCOM
2400[3] 0 – R/W
Configures all 6 SEG/COM pins as COM. Has no effect
on pins whose LCD_MAP bit is zero.
LCD_BAT
2402[7]
0
–
R/W
Connects the LCD power supply to VBAT in all modes.
LCD_E
2400[7] 0 – R/W
Enables the LCD display. When disabled, VLC2,
VLC1, and VLC0 are ground as are the COM and SEG
outputs if their LCD_MAP bit is 1.
LCD_ON
LCD_BLANK
240C[0]
240C[1]
0
0
–
R/W
R/W
LCD_ON = 1 turns on all LCD segments without
affecting the LCD data. Similarly, LCD_BLANK = 1
turns off all LCD segments without affecting the LCD
data. If both bits are set, all LCD segments are turned
on.
LCD_RST
240C[2] 0 – R/W
Clear all bits of LCD data. These bits affect SEGDIO
pins that are configured as LCD drivers.
LCD_DAC[4:0]
240D[4:0] 0 – R/W
This register controls the LCD contrast DAC, which
adjusts the VLCD voltage and has an output range of
2.5 VDC to 5 VDC. The VLCD voltage is
VLCD = 2.5 + 2.5 * LCD_DAC[4:0]/31
Thus, the LSB of the DAC is 80.6 mV. The maximum
DAC output voltage is limited by V3P3SYS, VBAT, and
whether LCD_BSTE is set.
LCD_CLK[1:0]
2400[1:0] 0 – R/W
Sets the LCD clock frequency (1/T). See definition of T
in Figure 21. Note: fw = 32768 Hz
00-fw/2^9, 01-fw/2^8, 10-fw/2^7, 11-fw/2^6
LCD_MODE[2:0]
2400[6:4] 0 – R/W
The LCD bias and multiplex mode.
LCD_MODE
Output
000
4 states, 1/3 bias
001
3 states, 1/3 bias
010
2 states, ½ bias
011
3 states, ½ bias
100
Static display
101
5 states, 1/3 bias
110
6 states, 1/3 bias
LCD_VMODE[1:0]
2401[7:6] 00 00 R/W
This register specifies how VLCD is generated.
LCD_VMODE
Description
11
External VLCD
10
LCD boost and LCD DAC
enabled
01
LCD DAC enabled
00
No boost and no DAC. VLCD
= VBAT or V3P3SYS
The LCD can be driven in static, ½ bias, and 1/3 bias modes. Figure 21 defines the COM waveforms.
Note that COM pins that are not required in a specific mode maintain a ‘segment off’ state rather than
GND, VCC, or high impedance.
The segment drivers SEGDIO22 and SEGDIO23 can be configured to blink at either 0.5 Hz or 1 Hz.
The blink rate is controlled by LCD_Y (I/O RAM 0x2400[2]). There can be up to six pixels/segments
connected to each of these driver pins. The I/O RAM fields LCD_BLKMAP22[5:0] (I/O RAM 0x2402[5:0])
and LCD_BLKMAP23[5:0] (I/O RAM 0x2401[5:0]) identify which pixels, if any, are to blink.
LCD_BLKMAP22[5:0] and LCD_BLKMAP23[5:0] are non-volatile.