Datasheet

71M6541D/F/G and 71M6542F/G Data Sheet
88 Rev 4
Table 69: Wake Enables and Flag Bits
Wake Enable
Wake Flag
De-bounce Description
Name
Location
Name
Location
WAKE_ARM
28B2[5]
WF_TMR
28B1[5]
No
Wake on Timer.
EW_PB
28B3[3]
WF_PB
28B1[3] Yes Wake on PB*.
EW_RX
28B3[4]
WF_RX
28B1[4]
2 µs
Wake on either edge of RX.
EW_DIO4
28B3[2]
WF_DIO4
28B1[2]
2 µs
Wake on SEGDIO4.
EW_DIO52†
28B3[1]
WF_DIO52
28B1[1] Yes Wake on SEGDIO52*.
EW_DIO55
28B3[0]
WF_DIO55
28B1[0] Yes
OPT_RXDIS = 1: Wake on DIO55*
with 64 ms de-bounce.
OPT_RXDIS = 0: Wake on either
edge of OPT_RX with 2 µs de-
bounce.
OPT_RXDIS: I/O RAM 0x2457[2]
Always Enabled
WF_RST
28B0[6]
2 µs
Wake after RESET.
Always Enabled
WF_RSTBIT
28B0[5]
No
Wake after RESET bit.
Always Enabled
WF_ERST
28B0[3] 2 µs
Wake after E_RST.
(ICE must be enabled)
Always Enabled
WF_OVF
28B0[4]
No
Wake after WD reset.
Always Enabled
WF_CSTART
28B0[7] No
Wake after cold start - the first
application of power.
Always Enabled
WF_BADVDD
28B0[2] No
Wake after insufficient VBAT
voltage.
† 71M6542F/G only.
*This pin is sampled every 2 ms and must remain high for 64 ms to be declared a valid high level. This
pin is high-level sensitive.