Datasheet

71M6543F/71M6543G Data Sheet
v2 35
Table 14: Port Registers (SEGDIO0-15)
SFR
Name
SFR
Address
D7 D6 D5 D4 D3 D2 D1 D0
P0
80
DIO_DIR[3:0]
DIO[3:0]
P1
90
DIO_DIR[7:4]
DIO[7:4]
P2
A0
DIO_DIR[11:8]
DIO[11:8]
P3
B0
DIO_DIR[15:12]
DIO[15:11]
All DIO ports on the chip are bi-directional. Each of them consists of a latch (SFR P0 to P3), an output
driver and an input buffer, therefore the MPU can output or read data through any of these ports. Even if
a DIO pin is configured as an output, the state of the pin can still be read by the MPU, for example when
counting pulses issued via DIO pins that are under CE control.
At power-up SEGDIO0-15 are configured as outputs, but the pins are in a high-impedance state
because PORT_E = 0 (I/O RAM 0x270C[5]). Host firmware should first configure SEGDIO0-15 to
the desired state, then set PORT_E = 1 to enable the function.
Clock Stretching (CKCON[2:0], SFR 0x8E)
The CKCON[2:0] field defines the stretch memory cycles that are used for MOVX instructions when
accessing external peripherals. The practical value of this register for the 71M6543 is to guarantee access
to XRAM between CE, MPU, and SPI. The default setting of CKCON[2:0] (001) should be changed to 000
for best performance.
Table 15 shows how the signals of the External Memory Interface change when stretch values are set
from 0 to 7. The widths of the signals are counted in MPU clock cycles. The post-reset state of the
CKCON[2:0] field (001), which is shown in bold in the table, performs the MOVX instructions with a
stretch value equal to 1.
Table 15: Stretch Memory Cycle Width
CKCON[2:0]
Stretch
Value
Read Signal Width Write Signal Width
memaddr
memrd
memaddr
memwr
000
0
1
1
2
1
001
1
2
2
3
1
010
2
3
3
4
2
011
3
4
4
5
3
100
4
5
5
6
4
101
5
6
6
7
5
110
6
7
7
8
6
111
7
8
8
9
7
2.4.4 Instruction Set
All instructions of the generic 8051 microcontroller are supported. A complete list of the instruction set
and of the associated op-codes is contained in the 71M654x Software User’s Guide (SUG).
2.4.5 UARTs
The 71M6543 include a UART (UART0) that can be programmed to communicate with a variety of AMR
modules and other external devices. A second UART (UART1) is connected to the optical port, as
described in the 2.5.9 UART and Optical Interface on page 56.
The UARTs are dedicated 2-wire serial interfaces, which can communicate with an external host processor
at up to 38,400 bits/s (with MPU clock = 1.2288 MHz). The operation of the RX and TX UART0 pins is as
follows: