Datasheet

71M6543F/71M6543G Data Sheet
v2 51
2.5.4.3 RTC Rate Control
The 71M6543 has two rate adjustment mechanisms:
• The first rate adjustment mechanism is an analog rate adjustment, using the I/O RAM register
RTCA_ADJ[6:0], that trims the crystal load capacitance.
• The second rate adjustment mechanism is a digital rate adjust that affects the way the clock frequency
is processed in the RTC.
Setting RTCA_ADJ[6:0] to 00 minimizes the load capacitance, maximizing the oscillator frequency. Setting
RTCA_ADJ[6:0] to 0x7F maximizes the load capacitance, minimizing the oscillator frequency. The adjustable
capacitance is approximately:
pF
ADJRTCA
C
ADJ
5.16
128
_
⋅=
The precise amount of adjustment depends on the crystal properties, the PCB layout and the value of the
external crystal capacitors (see CXS and CXS in Table 87). The adjustment may occur at any time, and the
resulting clock frequency should be measured over a one-second interval.
The second rate adjustment is digital, and can be used to adjust the clock rate up to ±988ppm, with a
resolution of 3.8 ppm. The rate adjustment is implemented starting at the next second-boundary
following the adjustment. Since the LSB (define first) results in an adjustment every four seconds, the
frequency should be measured over an interval that is a multiple of four seconds.
The clock rate is adjusted by writing the appropriate values to RTC_P[16:0] (I/O RAM 0x289B[2:0], 0x289C,
0x289D[7:2]) and RTC_Q[1:0] (I/O RAM 0x289D[1:0]). Updates to RTC rate adjust registers, RTC_P and
RTC_Q, are done through the shadow register described above. The new values are loaded into the
counters when RTC_WR (I/O RAM 0x2890[7]) is lowered.
The default frequency is 32,768 RTCLK cycles per second. To shift the clock frequency by ∆ ppm,
RTC_P and RTC_Q are calculated using the following equation:






+
⋅∆+
⋅
=+⋅
−
5.0
101
832768
RTC_QRTC_P4
6
floor
Conversely, the amount of ppm shift for a given value of 4RTC_P+RTC_Q is:
6
101
4
832768
)( ⋅








−
+⋅
⋅
=∆
QP
RTCRTC
ppm
For example, for a shift of -988 ppm, 4 ⋅ RTC_P + RTC_Q = 262403 = 0x40103. RTC_P[16:0] = 0x10040,
(I/O RAM 0x289B[2:0], 0x289C, 0x289D[7:2]) and RTC_Q[1:0] = 0x03 (I/O RAM 0x289D[1:0]. The default
values of RTC_P[16:0] and RTC_Q[1:0], corresponding to zero adjustment, are 0x10000 and 0x0, respectively.
Two settings for the TMUX2OUT test pin, PULSE_1S and PULSE_4S, are available for measuring and
calibrating the RTC clock frequency. These are waveforms of approximately 25% duty cycle with 1s or 4s
period.
Default values for RTCA_ADJ[6:0], RTC_P[16:0] and RTC_Q[1:0] should be nominal values, at
the center of the adjustment range. Un-calibrated extreme values (zero, for example) can cause
incorrect operation.
If the crystal temperature coefficient is known, the MPU can integrate temperature and correct the RTC
time as necessary. Alternatively, the characteristics can be loaded into an NV RAM and the OSC_COMP
(I/O RAM 0x28A0[5]) bit may be set. In this case, the oscillator is adjusted automatically, even in SLP
mode. See 2.5.4.4 RTC Temperature Compensation for details.