Datasheet
71M6543F/71M6543G Data Sheet
v2 53
For proper operation, the MPU has to load the lookup table with values that reflect the crystal properties
with respect to temperature, which is typically done once during initialization. Since the lookup table is
not directly addressable, the MPU uses the following procedure to load the NV RAM table:
1. Set the LKPAUTOI bit (I/O RAM 0x2887[7]) to enable address auto-increment.
2. Write zero into the I/O RAM register LKPADDR[6:0] (I/O RAM 0x2887[6:0]).
3. Write the 8-bit datum into I/O RAM register LKPDAT (I/O RAM 0x2888).
4. Set the LKP_WR bit (I/O RAM 0x2889[0]) to write the 8-bit datum into NV_RAM
5. Wait for LKP_WR to clear (LKP_WR auto-clears when the data has been copied to NV RAM).
6. Repeat steps 3 through 5 until all data has been written to NV RAM.
The NV RAM table can also be read by writing a 1 into the LKP_RD bit (I/O RAM 0x2889[1]). The process
of reading from and writing to the NV RAM is accelerated by setting the LKPAUTOI bit (I/O RAM 0x2887[7]).
When LKPAUTOI is set, LKPADDR[6:0] (I/O RAM 0x2887[6:0]) auto-increments every time LKP_RD or
LKP_WR is pulsed. It is also possible to perform random access of the NV RAM by writing a 0 to the
LKPAUTOI bit and loading the desired address into LKPADDR[6:0].
If the oscillator temperature compensation feature is not being used, it is possible to use the NV
RAM storage area as ordinary battery-backed NV storage space using the procedure described
above to read and write NV RAM data. In this case, the OSC_COMP bit (I/O RAM 0x28A0[5]) is
reset to disable the automatic oscillator temperature compensation feature.
2.5.4.5 RTC Interrupts
The RTC generates interrupts each second and each minute. These interrupts are called RTC_1SEC
and RTC_1MIN. In addition, the RTC functions as an alarm clock by generating an interrupt when the
minutes and hours registers both equal their respective target counts as defined in Table 44. The alarm
clock interrupt is called RTC_T. All three interrupts appear in the MPU’s external interrupt 6. See Table 32
in the interrupt section for the enable bits and flags for these interrupts.
The minute and hour target registers are listed in Table 44.
Table 44: I/O RAM Registers for RTC Interrupts
Name Location Rst Wk Dir
Description
RTC_TMIN[5:0]
289E[5:0]
0
0
R/W
The target minutes register. See below.
RTC_THR[4:0]
289F[4:0] 0 0 R/W
The target hours register. The RTC_T interrupt occurs
when RTC_MIN[5:0] becomes equal to RTC_TMIN[5:0]
and RTC_HR[4:0] becomes equal to RTC_THR[4:0].
2.5.5 71M6543 Temperature Sensor
The 71M6543 includes an on-chip temperature sensor for determining the temperature of its bandgap
reference. The primary use of the temperature data is to determine the magnitude of compensation
required to offset the thermal drift in the system for the compensation of current, voltage and energy
measurement and the RTC. See 4.5 Metrology Temperature Compensation on page 88. Also see 2.5.4.4
RTC Temperature Compensation on page 52.
Unlike earlier generation Maxim SoCs, the 71M6543 does not use the ADC to read the temperature
sensor. Instead, it uses a technique that is operational in SLP and LCD mode, as well as BRN and MSN
modes. This means that the temperature sensor can be used to compensate for the frequency variation
of the crystal, even in SLP mode while the MPU is halted. See 2.5.4.4 RTC Temperature Compensation
on page 52.
In MSN and BRN modes, the temperature sensor is awakened on command from the MPU by setting the
TEMP_START (I/O RAM 0x28B4[6]) control bit. In SLP and LCD modes, it is awakened at a regular rate
set by TEMP_PER[2:0] (I/O RAM 0x28A0[2:0]).
The result of the temperature measurement is read from the two I/O RAM locations STEMP[10:3] (I/O
RAM 0x2881) and STEMP[2:0] (I/O RAM 0x2882[7:5]). Note that both of these I/O RAM locations must be