Datasheet

71M6543F/71M6543G Data Sheet
92 v2
corresponding sensor circuit (i.e., the CT and burden resistor for current channels or the resistor divider
network for the voltage channels).
In the 71M6543F and 71M6543G, the required VREF compensation coefficients PPMC and PPMC2 are
calculated from readable on-chip non-volatile fuses (see 4.5.2Temperature Coefficients for the
71M6543F). These coefficients are designed to achieve ±40 ppm/°C for VREF.
4.6 Connecting I
2
C EEPROMs
I
2
C EEPROMs or other I
2
C compatible devices should be connected to the DIO pins SEGDIO2 and
SEGDIO3, as shown in Figure 33.
Pullup resistors of roughly 10 kΩ to V3P3D (to ensure operation in BRN mode) should be used for both
SDCK and SDATA signals. The DIO_EEX (I/O RAM 0x2456[7:6]) field must be set to 01 in order to convert
the DIO pins SEGDIO2 and SEGDIO3 to I
2
C pins SCL and SDATA.
Figure 33: I
2
C EEPROM Connection
4.7 Connecting Three-Wire EEPROMs
µWire EEPROMs and other compatible devices should be connected to the DIO pins SEGDIO2 and
SEGDIO3, as described in 2.5.11 EEPROM Interface on page 65.
4.8 UART0 (TX/RX)
The UART0 RX pin should be pulled down by a 10 kΩ resistor and additionally protected by a 100 pF
ceramic capacitor, as shown in Figure 34.
Figure 34: Connections for UART0
TX
RX
71M6543
10 k
Ω
100 pF
RX
TX
DIO2
DIO3
EEPROM
SDCK
SDATA
V3P3D
10 k
Ω
10 k
Ω
71M6543