Datasheet

DS_1903_032 73M1903 Data Sheet
Rev. 2.1 11
Figure 4: Analog Block Diagram
Table 3: PLL Loop Filter Settings
FL PLLloop Filter Settings
0 R1=32 kΩ,C1=100 pF,C2=2.5 pF
1 R1=16 kΩ, C1=100 pF,C2=2.5 pF
2.2.1 Control Register (CTRL 11): Address 0Bh
Reset State 12h
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Ndvsr6 Ndvsr5 Ndvsr4 Ndvsr3 Ndvsr2 Ndvsr1 Ndvsr0
Ndvsr[6:0] represents the divisor. If Nrst{2:0] =0 this register is ignored.
2.2.2 Control Register (CTRL 12): Address 0Ch
Reset State 00h
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Nseq7 Nseq6 Nseq5 Nseq4 Nseq3 Nseq2 Nseq1 Nseq0
Nseq[7:0] represents the divisor sequence.