Datasheet

DS_1903_032 73M1903 Data Sheet
Rev. 2.1 3
Figures
Figure 1: Effect of the TYPE (FS mode) pin on FS with SckMode = 0 ....................................................... 7
Figure 2: Control Frame Position versus SPOS
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Figure 3: Serial Port Timing Diagram
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Figure 4: Analog Block Diagram
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Figure 5: Clock Generation
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Figure 6: Overall Receiver Frequency Response
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Figure 7: Rx Passband Response
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Figure 8: RXD Spectrum of 1 kHz Tone
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Figure 9: RXD Spectrum of 0.5 kHz, 1 kHz, 2 kHz, 3 kHz and 3.5 kHz Tones of Equal Amplitudes
......... 20
Figure 10: Frequency Response of TX Path for DC to 4 kHz in Band Signal
........................................... 21
Figure 11: Serial Port Data Timing
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Figure 12: 32-Pin QFN Pinout
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Figure 13: 20-Pin TSSOP Pin out
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Figure 14: 73M1903 Schematic
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Figure 14: 32-Pin QFN Mechanical Specifications
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Figure 15: 20-Pin TSSOP Mechanical Specifications
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Figure 16: NCO Block Diagram
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Figure 17: PLL Block Diagram
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Tables
Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles ....................................................... 4
Table 2: Memory Map
.............................................................................................................................. 8
Table 3: PLL Loop Filter Settings
........................................................................................................... 11
Table 4: Kvco versus Settings at Vc=1.6 V, 25 °C
.................................................................................. 13
Table 5: PLL Power Down
..................................................................................................................... 14
Table 6: Examples of NCO Settings
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Table 7: Clock Generation Register Settings for Fxtal = 27 MHz
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Table 8: Clock Generation Register Settings for Fxtal = 24.576 MHz
...................................................... 16
Table 9: Clock Generation Register Settings for Fxtal = 9.216 MHz ........................................................ 16
Table 10: Clock Generation Register Settings for Fxtal = 24.000 MHz
.................................................... 17
Table 11: Clock Generation Register Settings for Fxtal = 25.35 MHz
...................................................... 17
Table 12: Receive Gain
......................................................................................................................... 18
Table 13: Peak to RMS Ratios for Various Modulation Types
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Table 14: Serial I/F Timing
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Table 15: Reference Voltage Specifications
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Table 16: Maximum Transmit Levels
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Table 17: Receiver Performance Specifications
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Table 18: Transmitter Performance Specifications
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Table 19: 32-Pin QFN Pin Definitions
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Table 20: 20-Pin TSSOP Pin Definitions
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Table 21: Bill of Materials
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Table 22: Ordering Information
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