Datasheet

73M1866B/73M1966B Data Sheet DS_1x66B_001
36 Rev. 1.6
• In 8-bit mode, if either the control or the address frames do not correspond to a multiple of eight
SCLK cycles, the SPI state machine resets and the transaction is aborted. If the data frame is shorter
than eight SCLK cycles, the state machine resets and the transaction is aborted. If the data frame is
longer than eight SCLK cycles, while not being a multiple of eight cycles, the write/read transaction is
performed and the state machine resets.
• In 16-bit mode, if the control/address frame does not contain a multiple of eight SCLK cycles, the SPI
state machine resets and the transaction is aborted. If the data frame is shorter than eight SCLK
cycles, the state machine resets and the transaction is aborted. If the data frame is longer than eight
SCLK cycles, while not being a multiple of eight cycles, the write/read transaction is performed and
the state machine resets. This scheme can be used to reset the SPI if one looses track of frames.