Datasheet

DS_1x66B_001 73M1866B/73M1966B Data Sheet
Rev. 1.6 37
6 Control and Status Registers
Table 31 shows the 73M1x66B register map of addressable registers. The shaded cells indicate read-only
bits and cannot be modified. Reserved bits should be left in their default state. Accessing unspecified
registers should be avoided. Each register and bit is described in detail in the following sections.
For registers 0x12 through 0x1F, which are located in the Line-Side Device, there is a minimum time
between consecutive write transactions of 300 µs when using an 8 kHz sample rate.
Table 31: Control and Status Register Map
Address
(hex)
Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
02 10h TMEN
Reserved Reserved
Reserved Reserved ENLPW Reserved Reserved
03 E0h GPIO7 GPIO6 GPIO5 PCLKDT RGMON DET SYNL RGDT
04 E4h DIR7 DIR6 DIR5 Reserved REVHSD3 REVHSD2 REVHSD1 REVHSD0
05 1Bh ENGPIO7 ENGPIO6 ENGPIO5 ENPCLKDT ENAPOL ENDET ENSYNL ENRGDT
06 00h POL7 POL6 POL5 Reserved Reserved Reserved Reserved Reserved
07 00h Reserved Reserved Reserved Reserved Reserved Reserved DTST1 DTST0
08 00h TXDG -12 TXDG -6 TXDG +3.5 TXDG +2 TXDG +1 TXDG +0.5 TXDG +0.25 TXDG +0.125
09 00h RXDG -12 RXDG -6 RXDG +3.5 RXDG +2 RXDG +1 RXDG +0.5 RXDG +0.25 RXDG +0.125
0D 40h LOKDET SLHS Reserved Reserved
RSTLSBI
Reserved Reserved Reserved
0E 00h FRCVCO Reserved Reserved Reserved Reserved Reserved RGTH1 RGTH0
0F 80h ENFEH PWDN SLEEP Reserved Reserved Reserved Reserved Reserved
10 00h Reserved Reserved Reserved CMVSEL CMTXG1 CMTXG0 CMRXG1 CMRXG0
12 00h OFH ENDC ENAC ENSHL
ENLVD
ENFEL ENDT ENNOM
13 00h DCIV1 DCIV0 ILM Reserved PLDM OVDTH IDISPD SEL16K
14 00h TXBST DAA1 DAA0 Reserved RXBST RLPNH RXG1 RXG0
15 00h ENOLD DISNTR Reserved CIDM THEN ENUVD ENOVD ENOID
16 00h TXEN RXEN RLPNEN ATEN ACZ3 ACZ2 ACZ1 ACZ0
17 00h Reserved Reserved RXOCEN Reserved Reserved Reserved Reserved Reserved
18 01h TEST3 TEST2 TEST1 TEST0 Reserved Reserved Reserved Reserved
19 00h POLL MATCH Reserved Reserved INDX3 INDX2 INDX1 INDX0
1A 00h RNG7 RNG6 RNG5 RNG4 RNG3 RNG2 RNG1 RNG0
1B 00h LV7 LV6 LV5 LV4 LV3 LV2 LV1 Reserved
1C 00h LC6 LC5 LC4 LC3 LC2 LC1 LC0 Reserved
1D 00h REVLSD3 REVLSD2 REVLSD1 REVLSD0 Reserved Reserved Reserved Reserved
1E 00h ILMON UVDET OVDET OIDET OLDET SLLS Reserved Reserved
1F 00h POLVAL7 POLVAL6 POLVAL5 POLVAL4 POLVAL3 POLVAL2 POLVAL1 POLVAL0
20 00h TPOL TTS6 TTS5 TTS4 TTS3 TTS2 TTS1 TTS0
21 00h RPOL RTS6 RTS5 RTS4 RTS3 RTS2 RTS1 RTS0
22 00h SR ADJ RCS2 RCS1 RCS0 TCS2 TCS1 TCS0
23 00h PCMEN MASTER PCODE3 PCODE2 PCODE1 PCODE0 LIN LAW
24 00h Reserved Reserved Reserved Reserved Reserved Reserved Reserved LB
25 00h RXOM7 RXOM6 RXOM5 RXOM4 RXOM3 RXOM2 RXOM1 RXOM0