Datasheet

DS_1x66B_001 73M1866B/73M1966B Data Sheet
Rev. 1.6 41
7 Hardware Control Functions
This section describes the 73M1x66B capabilities with respect to its configuration and hardware pin
control. These include features such as Device Revision, Interrupt Management, Power Management,
Clock Control, General Purpose Input/Output (GPIO) and control of the Call Progress Monitor.
7.1 Device Revision
The 73M1x66B provides the device revision number for the Host-Side Device and the Line-Side Device.
For the 73M1x66B:
• Revision for the Host-Side Device is: 0100.
• Revision for the Line-Side Device is: 1101.
Function
Mnemonic
Register
Location
Type Description
REVHSD 0x04[3:0] R Host-Side Device Revision
These read only status bits indicate the revision of the 73M1x66B
Host-Side Device (73M1906B).
REVLSD 0x1D[7:4] R Line-Side Device Revision
These read-
only status bits provide the Device ID for the 73M1x66B
Line-Side Device (73M1916).
When barrier is synchronized, REV has the value of 1101.
When barrier is not synchronized, the value of the field is 0000.
7.2 Interrupt Control
The 73M1x66B supports a single interrupt that can be asserted under several configurable conditions.
These include status of GPIOs, PCLKDT, RGMON, DET, SYNL and RGDT.
All interrupt sources that are enabled are ORed together to create the INT output signal. GPIO ports that
are configured to be output will not generate interrupts.
When the INT pin goes active (low), the host should read the interrupt source Register 0x03, which is
then automatically cleared after the read operation. An interrupt during wake-on-ring should be
interpreted as the detection of a valid ring signal.
Address 0x03
Reset State E0h
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
GPIO7 GPIO6 GPIO5 PCLKDT RGMON DET SYNL RGDT