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73M1866B/73M1966B Data Sheet DS_1x66B_001

52 Rev. 1.6

8.8 PCM Control Functions

Table 33: PCM Control Functions

Function

Mnemonic

Location

Type Description

ADJ 0x22[6] W Adjacent Time Slot Driver Control

Allows LSB of the PCM frame (DX) to be tri-stated during the second

half of the clock cycle. This feature allows adjacent time slots to be

used by different devices without risking a contention at the time slot

boundary.

0 = Drives DX during the entire bit time. (Default)

1 = Drives DX only during the first half of bit time.

DAA 0x14[6:5] W DAA Transmit Gain

Used in conjunction with TXBST to manage transmit level. See

Section 8.8.1.

ENPCLKDT 0x05[4] W Enable PCLK Error Detection Interrupt

0 = Disables this function.

1 = Enables the detection of an interrupt resulting from an

incoherency in the PCLK count during the second set of eight

frames received after power up. (Default)

LAW 0x23[0] W Law Compression Mode

Selects the PCM compression mode.

0 = Selects the A-law compression mode. (Default)

1 = Selects the μ-law compression mode.

LIN 0x23[1] W Linear Mode Enable

0 = The compression modes of either A-law or μ-law are enabled.

(Default.) See the LAW bit.

1 = 16-bit linear mode.

MASTER 0x23[6] W Master/Slave Mode

The 73M1x66B is in Slave Mode by default. See Section 8.3 for

details of master and slave operation.

0 = Enables Slave Mode. (Default)

1 = Enables Master Mode.

PCLKDT 0x03[4] R PCLK Detect Error

PCLKDT is an interrupt resulting from the detection of two possible

events:

1. The number of PCLK periods per frame is not consistent among

the second set of eight frames after power up.

2. The number of PCLK periods per frame does not equate to any

of the acceptable PCLK frequencies. This is a maskable interrupt. It

is enabled by the ENPCLKDT bit. See Section 7.2.

PCMEN 0x23[7] W PCM Transmit Enable

Controls DX and TSC. This bit must be set on completion of all

configuration changes to enable transmission on to the PCM

highway.

When powered up, the 73M1x66B PCM outputs are tri-stated. The

host must set PCMEN after setting the time/clock slot control bits to

avoid contention on the PCM highway.