Datasheet

DS_1x66B_001 73M1866B/73M1966B Data Sheet

Rev. 1.6 53

Function

Mnemonic

Location

Type Description

PCODE 0x23[5:2] W PCM Clock Code

The default state of PCODE out of reset is 0000. In PCM Slave

Mode at reset, the device will attempt to automatically detect the

correct frequency of PCLK. If the PCLK frequency is different from

those listed in the table below or an incorrect PCODE value is

written, the PLL will not lock (LOCKDET 0x0D[7] == 0). To modify

the value of PCODE, first write a value of 0000 and then write the

required PCODE value. Toggling of the MASTER bit 0x23[6]

1  0) with a PCODE of 0000 will also restart the automatic

PCLK frequency detection function.

PCLK

Frequency

PCODE [3:0]

256 kHz 0001

512 kHz 0010

768 kHz 0011

1.024 MHz 0100

1.536 MHz 0101

1.544 MHz 0110

2.048 MHz 0111

3.088 MHz 1000

4.096 MHz 1001

6.176 MHz 1010

8.192 MHz 1011

RCS 0x22[5:3] W Receive Clock Slot

These bits control the starting clock of the receive channel. The

clock slot value allows the adding of an offset of up to 7 (111) bits to

the time slot value. A value of 000 is zero offset.

RPOL 0x21[7] W Receive Polarity

0 = The receive PCM data is to be sampled on the falling edge of

PCLK. (Default)

1 = The receive PCM data is to be sampled on the rising edge of

PCLK.

RTS 0x21[6:0] W Receive Time Slot

Selects the time slot number on the PCM highway for the receiver.

The maximum number of 8-bit time slots is 128 (with a PCLK

frequency of 8.192 MHz). A value of 0000000 is time slot zero and

1111111 is time slot 128. The default is 0000000.