Datasheet

73M1866B/73M1966B Data Sheet DS_1x66B_001

62 Rev. 1.6

Function

Mnemonic

Location

Type Description

RSTLSBI 0x0D[3] W Reset Line-Side Barrier Interface

To reset the Line-Side Barrier Interface, set this bit to 1.

1 = Resets the Line-Side Barrier Interface. The chip sets this bit back

to 0 after it has completed resetting the Line-Side Barrier Interface.

SLHS 0x0D[6] R Synchronization Lost Host Side

This bit indicates the status of the Barrier Interface as seen from the

Host-Side.

0 = Host-Side Barrier Interface is synchronized.

1 = Host-Side Barrier Interface lost synchronization.

Once read, the SLHS bit is reset, but will be set again if the

synchronization loss continues.

SLLS

0x1E[2]

Synchronization Loss Line Side

0 = TXRDY will continuously be generated following Synchronization

Loss so as to allow

SLLS information to be transferred across the

barrier. This causes an automatic transfer of 1Eh. (Default)

1 = Synchronization is lost in the Line-Side Device due to Header.

SYNL 0x03[1] R Barrier Synchronization Loss

0 = Indicates synchronization of data across the barrier.

1 = Indicates a loss of synchronization of data across the barrier.

This status bit is reset when read. This is a maskable interrupt. It is

enabled by the ENSYNL bit.