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73S1215F

80515 System-on-Chip with USB,

ISO 7816 / EMV, PINpad and More

Simplifying System Integration™

DATA SHEET

December 2008

GENERAL DESCRIPTION

The 73S1215F is a versatile and economical

CMOS System-on-Chip device intended for smart

card reader applications. The circuit features an

ISO 7816 / EMV interface, an USB 2.0 interface

(full-speed 12Mbps device) and a 5x6 PINpad

interface. Maximum design flexibility is supported

with additional features such as 9 user I/Os,

multiple interrupt options, up to 4 programmable

current outputs (to drive external LEDs), and 1

analog voltage input (suitable for DC voltage

monitoring such as battery level detection). Other

built-in hardware interfaces include an

asynchronous serial UART and an I

C interface.

The System-on-Chip is built around an 80515 high

performance core. Its feature and instruction set is

compatible with the industry standard 8051, while

offering one clock-cycle per instruction processing

power (most instructions)With a CPU clock running

up to 24MHz, it results in up to 20 MIPS available

that meets the requirements of various encryption

needs such as AES, DES / 3-DES and even RSA

(for PIN encryption for instance). The circuit

requires a single crystal, which frequency can be

between 6MHz and 12MHz. In addition, a 32768

Hz sub-system oscillator (optional) with an

independent real-time-clock counter enables stand-

alone applications to access an RTC value. The

respective 73S1215F embedded memories are;

64KB Flash program memory, 2KB user XRAM

memory, and 256B IRAM memory. In addition to

these memories are independent FIFOs dedicated

to the ISO7816 UART and to the USB interface.

Overall, the 73S1215F offers a cost effective

solution to implement hand-held PINpad smart card

readers - USB connected, serial connected,

standalone or combo – as well as turnkey smart

card reader modules, USB or ExpressCard

type.

Embedded Flash memory is in-system

programmable and lockable by means of on-silicon

fuses. This makes the Teridian 73S1215F suitable

for both development and production phases.

Teridian Semiconductor Corporation offers with

its 73S1215F a very comprehensive set of

software libraries, including the smart card and

USB protocol layers that are pre-approved

against USB, Microsoft WHQL and EMV, as

well as a CCID reference design. Refer to the

73S12xxF Software User’s Guide for a

complete description of the Application

Programming Interface (API Libraries) and

related software modules.

A complete array of development and

programming tools, libraries and demonstration

boards enable rapid development and

certification of smart card readers that meet

most demanding smart card standards.

APPLICATIONS

• Hand-held PINpad smart card readers:

o Connected through USB, serial or

un-connected

o CCID-compliant

• E-banking (MasterCard CAP, etc)

• Smart card reader modules for PC laptops

and desktops: ExpressCard® , USB

• Digital Identification (Secure Login, Gov’t ID, ...)

• General purpose smart card readers

ADVANTAGES

• The ideal balance of cost and features for

high volume, USB-connected PINpad type

of applications:

o Larger built-in Flash / RAM than its

competitors

o Higher performance CPU core

o Powerful In-Circuit- Emulation and

Programming

o A complete set of ready-to-use EMV4.1 /

USB / CCID libraries

Summary of content (136 pages)

PAGE 1
73S1215F 80515 System-on-Chip with USB, ISO 7816 / EMV, PINpad and More Simplifying System Integration™ DATA SHEET December 2008 GENERAL DESCRIPTION The 73S1215F is a versatile and economical CMOS System-on-Chip device intended for smart card reader applications. The circuit features an ISO 7816 / EMV interface, an USB 2.0 interface (full-speed 12Mbps device) and a 5x6 PINpad interface.
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73S1215F Data Sheet DS_1215F_003 FEATURES 80515 Core: Communication Interfaces: • • • • • • • Single low-cost 6MHz to 12MHz crystal • Full-duplex serial interface (1200 to 115kbps UART) • USB 2.
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DS_1215F_003 73S1215F Data Sheet Table of Contents 1 Hardware Description ......................................................................................................................... 8 1.1 Pin Description .............................................................................................................................. 8 1.2 Hardware Overview .................................................................................................................... 11 1.3 80515 MPU Core .
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73S1215F Data Sheet DS_1215F_003 Figures Figure 1: IC Functional Block Diagram ......................................................................................................... 7 Figure 2: Memory Map ................................................................................................................................ 15 Figure 3: Clock Generation and Control Circuits ........................................................................................ 24 Figure 4: Oscillator Circuit .
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DS_1215F_003 73S1215F Data Sheet Tables Table 1: 73S1215F Pinout Description ......................................................................................................... 8 Table 2: MPU Data Memory Map................................................................................................................ 11 Table 3: Flash Special Function Registers ................................................................................................. 13 Table 4: Internal Data Memory Map ....
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73S1215F Data Sheet DS_1215F_003 Table 83: The 24-bit RTC Trim (sign magnitude value) .............................................................................. 54 Table 84: The INT5Ctl Register .................................................................................................................. 54 Table 86: The ACOMP Register ................................................................................................................. 55 Table 88: The INT6Ctl Register ................
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DS_1215F_003 73S1215F Data Sheet VPC TBUS0 TBUS1 TBUS2 RXTX TBUS3 ERST ISBR TCLK VDD ANA_IN SEC RESET TEST GND Table 181: The RLength Register ............................................................................................................. 108 Table 182: Smart Card SFR Table ........................................................................................................... 109 Table 183: The VDDFCtl Register ..............................................................
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73S1215F Data Sheet DS_1215F_003 1 Hardware Description 1.1 Pin Description Pin (68 Qfn) Pin (44 Qfn) Type Equivalent Circuit* Table 1: 73S1215F Pinout Description X12IN 10 8 I Figure 27 X12OUT X32IN 11 8 9 O I Figure 27 Figure 28 X32OUT CPUCLK 7 39 O O Figure 28 Figure 30 DP DM ROW(5:0) 0 1 2 3 4 5 COL(4:0) 0 1 2 3 4 USR(8:0) 0 1 2 3 4 5 6 7 8 SCL 26 27 IO IO I Figure 43 Figure 43 Figure 34 MPU/USB clock crystal oscillator input pin. A 12MHz crystal is required for USB operation.
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1 3 2 4 17 18 51 52 50 3 4 11 12 SCLK Equivalent Circuit* LED(3:0) 0 1 2 3 RXD TXD INT3 INT2 SIO Type Pin (44 Qfn) 73S1215F Data Sheet Pin (68 Qfn) DS_1215F_003 IO Figure 36 Special output drivers, programmable pull-down current to drive LEDs. May also be used as inputs.
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Pin (44 Qfn) Type Equivalent Circuit* DS_1215F_003 Pin (68 Qfn) 73S1215F Data Sheet ANA_IN 15 10 AI Figure 38 SEC 67 2 I Figure 37 TEST VDD 54 28 42 65 33 18 27 44 DI I Figure 37 N/C GND 46 9 25 44 29 7 15 0 GND RESET 66 1 I Pin Name Figure 33 Description Analog input pin. This signal goes to a programmable comparator and is used to sense the value of an external voltage. Input pin for use in programming security fuse. It should be connected to ground when not in use.
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DS_1215F_003 73S1215F Data Sheet 1.2 Hardware Overview The Teridian 73S1215F single smart card controller integrates all primary functional blocks required to implement a smart card reader. Included on chip are an 8051-compatible microprocessor (MPU) which executes up to one instruction per clock cycle (80515), a fully integrated IS0-7816 compliant smart card interface, expansion smart card interface, full speed USB 2.
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73S1215F Data Sheet DS_1215F_003 The mass erase sequence is: 1. Write 1 to the FLSH_MEEN bit in the FLSHCTL register (SFR address 0xB2[1]). 2. Write pattern 0xAA to ERASE (SFR address 0x94). Note: The mass erase cycle can only be initiated when the ICE port is enabled. The page erase sequence is: 1. Write the page address to PGADDR (SFR address 0xB7[7:1]). 2. Write pattern 0x55 to ERASE (SFR address 0x94). The PGADDR register denotes the page address for page erase.
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DS_1215F_003 73S1215F Data Sheet Table 3: Flash Special Function Registers Register ERASE SFR Address R/W 0x94 W Description This register is used to initiate either the Flash Mass Erase cycle or the Flash Page Erase cycle. Specific patterns are expected for ERASE in order to initiate the appropriate Erase cycle (default = 0x00). 0x55 – Initiate Flash Page Erase cycle. Must be proceeded by a write to PGADDR @ SFR 0xB7. 0xAA – Initiate Flash Mass Erase cycle.
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73S1215F Data Sheet DS_1215F_003 Internal Data Memory: The Internal data memory provides 256 bytes (0x00 to 0xFF) of data memory. The internal data memory address is always one byte wide and can be accessed by either direct or indirect addressing. The Special Function Registers occupy the upper 128 bytes. This SFR area is available only by direct addressing. Indirect addressing accesses the upper 128 bytes of Internal RAM. The lower 128 bytes contain working registers and bit-addressable memory.
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DS_1215F_003 Address Use 0xFFFF 73S1215F Data Sheet Address Use 0xFFFF Peripheral Control Registers (128b) 0XFF80 0xFF7F 0XFE00 0xFDFF 0XFC00 0xFBFF 0x0800 Smart Card Control (384b) USB Registers (512b) – Use Address 0x07FF 0xFF Flash Program Memory 0x80 Indirect Access Direct Access Byte RAM SFRs 0x7F 64K Bytes Byte RAM 0x48 0x47 XRAM Bit/Byte RAM 0x20 0x1F Register bank 3 0x18 0x17 Register bank 2 0x10 0x0F Register bank 1 0x08 0x07 0x0000 Program Memory 0x0000 Register ba
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73S1215F Data Sheet DS_1215F_003 1.4 Program Security Two levels of program and data security are available. Each level requires a specific fuse to be blown in order to enable or set the specific security mode. Mode 0 security is enabled by setting the SECURE bit (bit 6 of SFR register FLSHCTL 0xB2) Mode 0 limits the ICE interface to only allow bulk erase of the flash program memory. All other ICE operations are blocked. This guarantees the security of the user’s MPU program code.
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DS_1215F_003 73S1215F Data Sheet Table 5: Program Security Registers Register SFR Address R/W Description FLSHCTL 0xB2 R/W Bit 0 (FLSH_PWE): Program Write Enable: 0 – MOVX commands refer to XRAM Space, normal operation (default). 1 – MOVX @DPTR,A moves A to Program Space (Flash) @ DPTR. This bit is automatically reset after each byte written to flash. Writes to this bit are inhibited when interrupts are enabled. W Bit 1 (FLSH_MEEN): Mass Erase Enable: 0 – Mass Erase disabled (default).
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73S1215F Data Sheet DS_1215F_003 1.5 Special Function Registers (SFRs) The 73S1215F utilizes numerous SFRs to communicate with the 73S1215F s many peripherals. This results in the need for more SFR locations outside the direct address IRAM space (0x80 to 0xFF). While some peripherals are mapped to unused IRAM SFR locations, additional SFRs for the USB, smart card and other peripheral functions are mapped to the top of the XRAM data space (0xFC00 to 0xFFFF). 1.5.
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DS_1215F_003 1.5.2 73S1215F Data Sheet IRAM Special Function Registers (Generic 80515 SFRs) Table 7 shows the location of the SFRs and the value they assume at reset or power-up.
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73S1215F Data Sheet DS_1215F_003 PSW 0xD0 0x00 Program Status Word KCOL 0XD1 0x1F Keypad Column KROW 0XD2 0x3F Keypad Row KSCAN 0XD3 0x00 Keypad Scan Time KSTAT 0XD4 0x00 Keypad Control/Status KSIZE 0XD5 0x00 Keypad Size KORDERL 0XD6 0x00 Keypad Column LS Scan Order KORDERH 0XD7 0x00 Keypad Colum MS Scan Order BRCON 0xD8 0x00 Baud Rate Control Register (only BRCON.7 bit used) A 0xE0 0x00 Accumulator B 0xF0 0x00 B Register 1.5.
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DS_1215F_003 73S1215F Data Sheet Name Location Reset Value Description TRIMPCtl 0x FFD1 0x00 TRIM Pulse Control FUSECtl 0x FFD2 0x00 FUSE Control VDDFCtl 0x FFD4 0x00 VDDFault Control SECReg 0x FFD7 0x00 Security Register MISCtl0 0x FFF1 0x00 Miscellaneous Control Register 0 MISCtl1 0x FFF2 0x10 Miscellaneous Control Register 1 LEDCtl 0x FFF3 0xFF LED Control Register Accumulator (ACC, A): ACC is the accumulator register.
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73S1215F Data Sheet DS_1215F_003 Program Status Word (PSW): Table 9: PSW Register Flags MSB LSB CV AC F0 RS1 RS OV – P Table 10: PSW Bit Functions Bit Symbol Function PSW.7 CV Carry flag. PSW.6 AC Auxiliary Carry flag for BCD operations. PSW.5 F0 General purpose Flag 0 available for user. PSW.4 RS1 Register bank select control bits. The contents of RS1 and RS0 select the working register bank: RS1/RS0 PSW.
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DS_1215F_003 73S1215F Data Sheet Table 11: Port Registers SFR Address R/W USR70 0x90 R/W Register for User port bit 7:0 read and write operations (pins USR0… USR7). UDIR70 0x91 R/W Data direction register for User port bits 0:7. Setting a bit to 0 means that the corresponding pin is an output. USR8 0xA0 R/W Register for User port bit 8 read and write operations (pin *USR8). UDIR8 0xA1 R/W Data direction register for port 1. Register Description All ports on the chip are bi-directional.
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73S1215F Data Sheet DS_1215F_003 MCount(2:0) X12IN HOSCen 12.00MHz USBCKenb HIGH XTAL OSC HCLK M DIVIDER /(2*N + 4) 12.00MHz X32IN 32768Hz LOW XTAL OSC USBCLK 48MHz div 2 X12OUT DIVIDER /2930 Phase Freq DET VCO MCLK 96MHz LMCLK=32765Hz X32OUT RTCCLK Mux LCLK=32768Hz DIV 32 32KOSCenb CPU CLOCK DIVIDER 6 bits 1.5-48MHz 1kHz ICLK 7.386MHz 7.386MHz MPU CLOCK - CPCLK 3.
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DS_1215F_003 73S1215F Data Sheet The master clock control register enables different sections of the clock circuitry and specifies the value of the VCO Mcount divider. The MCLK must be configured to operate at 96MHz to ensure proper operation of some of the peripheral blocks according to the following formula: MCLK = (Mcount * 2 + 4) * FXTAL = 96MHz Mcount is configured in the MCLKCtl register must be bound between a value of 1 to 7.
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73S1215F Data Sheet DS_1215F_003 MPU Clock Control Register (MPUCKCtl): 0xFFA1 Å 0x0C Table 14: The MPUCKCtl Register MSB LSB – – Bit Symbol MPUCKCtl.7 – MPUCKCtl.6 – MPUCKCtl.5 MDIV.5 MPUCKCtl.4 MDIV.4 MPUCKCtl.3 MDIV.3 MPUCKCtl.2 MDIV.2 MPUCKCtl.1 MDIV.1 MPUCKCtl.0 MDIV.0 MDIV.5 MDIV.4 MDIV.3 MDIV.2 MDIV.1 MDIV.0 Function This value determines the ratio of the MPU master clock frequency to the VCO frequency (MCLK) such that MPUClk = MCLK/(2 * (MPUCKDiv(5:0) + 1)).
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DS_1215F_003 1.7.2 73S1215F Data Sheet Power Control Modes The 73S1215F contains circuitry to disable portions of the device and place it into a lower power standby mode. This is accomplished by either shutting off the power or disabling the clock going to the block. The miscellaneous control registers MISCtl0, MISCtl1 and the master clock control register (MCLKCtl) provide control over the power modes.
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73S1215F Data Sheet DS_1215F_003 PDMUX (FF94h:bit7) USR0 USR1 USR2 USR3 USR4 USR5 USR6 USR7 USR[7:0] Control MPU 0 USRxINTSrc set to 4(ext INT0 high) or 6(ext INT0 low) INT0 1 INT4 CE INT5 TC 9 BIT CNTR CLR RESETB D Q PWRDN (FFF1h:bit7) PWRDN_analog CLR TC CE RESETB Notes: 1. The counters are clocked by the MPUCLK 2. TC - Terminal count (high at overflow) 3.
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DS_1215F_003 73S1215F Data Sheet External Interrupt Control Register (INT5Ctl): 0xFF94 Å 0x00 Table 15: The INT5Ctl Register MSB LSB PDMUX Bit – RTCIEN RTCINT USBIEN USBINT KPIEN KPINT Symbol Function INT5Ctl.7 PDMUX When set = 1, enables interrupts from USB, RTC, Keypad (normally going to int5), Smart Card interrupts (normally going to int4), or USR(7:0) pins (int0) to cause interrupt on int0.
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73S1215F Data Sheet DS_1215F_003 Miscellaneous Control Register 1 (MISCtl1): 0xFFF2 Å 0x10 Table 17: The MISCtl1 Register MSB LSB – – Bit Symbol MISCtl1.7 – MISCtl1.6 – FRPEN FLSH66 – ANAPEN USBPEN USBCON Function MISCtl1.5 FRPEN Flash Read Pulse enable (low). If FRPEN = 1, the Flash Read signal is passed through with no change. When FRPEN = 0 a one-shot circuit that shortens the Flash Read signal is enabled to save power.
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DS_1215F_003 73S1215F Data Sheet Master Clock Control Register (MCLKCtl): 0x8F Å 0x0A Table 18: The MCLKCtl Register MSB LSB HSOEN KBEN SCEN USBEN 32KEN MCT.2 MCT.1 MCT.0 Bit Symbol Function MCLKCtl.7 HSOEN* MCLKCtl.6 KBEN 1 = Disable the keypad logic clock. This bit is not changed in PWRDN mode but the function is disabled. MCLKCtl.5 SCEN 1 = Disable the smart card logic clock. This bit is not changed in PWRDN mode but the function is disabled.
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73S1215F Data Sheet DS_1215F_003 Power Control Register 0 (PCON): 0x87 Å 0x00 The SMOD bit used for the baud rate generator is setup via this register. Table 19: The PCON Register MSB LSB SMOD 32 – – – Bit Symbol PCON.7 SMOD PCON.6 – PCON.5 – PCON.4 – PCON.3 GF1 General purpose flag 1. PCON.2 GF0 General purpose flag 1. PCON.1 STOP Sets CPU to Stop mode. PCON.0 IDLE Sets CPU to Idle mode. GF1 GF0 STOP IDLE Function If SM0D = 1, the baud rate is doubled. Rev. 1.
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DS_1215F_003 1.7.3 73S1215F Data Sheet Interrupts The 80515 core provides 10 interrupt sources with four priority levels. Each source has its own request flag(s) located in a special function register (TCON, IRCON, and SCON). Each interrupt requested by the corresponding flag can be individually enabled or disabled by the enable bits in SFRs IEN0, IEN1 and IEN2. Some of the 10 sources are multiplexed in order to expand the number of interrupt sources.
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73S1215F Data Sheet 1.7.3.1 DS_1215F_003 Interrupt Overview When an interrupt occurs, the MPU will vector to the predetermined address as shown in Table 33. Once the interrupt service has begun, it can only be interrupted by a higher priority interrupt. The interrupt service is terminated by a return from the REIT instruction. When a RETI is performed, the processor will return to the instruction that would have been next when the interrupt occurred.
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DS_1215F_003 73S1215F Data Sheet Interrupt Enable 1 Register (IEN1): 0xB8 Å 0x00 Table 21: The IEN1 Register MSB – LSB SWDT EX6 EX5 EX4 EX3 Bit Symbol IEN1.7 – IEN1.6 SWDT IEN1.5 EX6 EX6 = 0 – disable external interrupt 6. IEN1.4 EX5 EX5 = 0 – disable external interrupt 5. IEN1.3 EX4 EX4 = 0 – disable external interrupt 4. IEN1.2 EX3 EX3 = 0 – disable external interrupt 3. IEN1.1 EX2 EX2 = 0 – disable external interrupt 2. IEN1.
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73S1215F Data Sheet DS_1215F_003 Timer/Counter Control Register (TCON): 0x88 Å 0x00 Table 23: The TCON Register MSB TF1 LSB TR1 TF0 TR0 IE1 IT1 IE0 IT0 Bit Symbol Function TCON.7 TF1 Timer 1 overflow flag. TCON.6 TR1 Not used for interrupt control. TCON.5 TF0 Timer 0 overflow flag. TCON.4 TR0 Not used for interrupt control. TCON.3 IE1 Interrupt 1 edge flag is set by hardware when the falling edge on external interrupt int1 is observed. Cleared when an interrupt is processed.
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DS_1215F_003 73S1215F Data Sheet Interrupt Request Register (IRCON): 0xC0 Å 0x00 Table 25: The IRCON Register MSB LSB – – EX6 IEX5 Bit Symbol IRCON.7 – IRCON.6 – IRCON.5 IEX6 External interrupt 6 flag. IRCON.4 IEX5 External interrupt 5 flag. IRCON.3 IEX4 External interrupt 4 flag. IRCON.2 IEX3 External interrupt 3 flag. IRCON.1 IEX2 External interrupt 2 flag. IRCON.0 – 1.7.3.
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73S1215F Data Sheet DS_1215F_003 Table 27: Control Bits for External Interrupts Enable Bit 1.7.3.
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DS_1215F_003 73S1215F Data Sheet Interrupt Priority 1 Register (IP1): 0xB9 Å 0x00 Table 30: The IP1 Register MSB – LSB – IP1.5 IP1.4 IP1.3 IP1.2 IP1.1 IP1.0 Table 31: Priority Levels IP1.x IP0.
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73S1215F Data Sheet 1.7.4 DS_1215F_003 UART The 80515 core of the 73S1215F includes two separate UARTs that can be programmed to communicate with a host. The 73S1215F can only connect one UART at a time since there is only one set of TX and Rx pins. The MISCtl0 register is used to select which UART is connected to the TX and RX pins. Each UART has a different set of operating modes that the user can select according to their needs.
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DS_1215F_003 73S1215F Data Sheet Power Control Register 0 (PCON): 0x87 Å 0x00 The SMOD bit used for the baud rate generator is set up via this register. Table 36: The PCON Register MSB LSB SMOD – – – GF1 GF0 Bit Symbol Function PCON.7 SMOD If SM0D = 1, the baud rate is doubled. PCON.6 – PCON.5 – PCON.4 – PCON.3 GF1 General purpose flag 1. PCON.2 GF0 General purpose flag 1. PCON.1 STOP Sets CPU to Stop mode. PCON.0 IDLE Sets CPU to Idle mode.
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73S1215F Data Sheet DS_1215F_003 Miscellaneous Control Register 0 (MISCtl0): 0xFFF1 Å 0x00 Transmit and receive (TX and RX) pin selection and loop back test configuration are set up via this register. Table 38: The MISCtl0 Register MSB LSB PWRDN – Bit Symbol MISCtl0.7 PWRDN MISCtl0.6 – MISCtl0.5 – MISCtl0.4 – MISCtl0.3 – MISCtl0.2 – – – – – SLPBK SSEL Function This bit places the 73S1215F into a power down state. MISCtl0.1 SLPBK 1 = UART loop back testing mode.
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DS_1215F_003 73S1215F Data Sheet Serial Interface 0 Control Register (S0CON): 0x9B Å 0x00 Transmit and receive data are transferred via this register. Table 39: The S0CON Register MSB LSB SM0 SM1 SM20 REN0 TB80 RB80 TI0 RI0 Bit Symbol Function S0CON.7 SM0 These two bits set the UART0 mode: S0CON.6 SM1 Mode Description SM0 SM1 0 N/A 0 0 1 8-bit UART 0 1 2 9-bit UART 1 0 3 9-bit UART 1 1 S0CON.5 SM20 Enables the inter-processor communication feature. S0CON.
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73S1215F Data Sheet DS_1215F_003 Serial Interface Control Register (S1CON): 0x9B Å 0x00 The function of the serial port depends on the setting of the Serial Port Control Register S1CON. Table 40: The S1CON Register MSB LSB SM – Bit Symbol S1CON.7 SM SM21 REN1 TB81 RB81 TI1 RI1 Function Sets the UART operation mode. SM Mode Description Baud Rate 0 A 9-bit UART variable 1 B 8-bit UART variable S1CON.6 – S1CON.5 SM21 Enables the inter-processor communication feature. S1CON.
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DS_1215F_003 1.7.5 73S1215F Data Sheet Timers and Counters The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be configured for counter or timer operations. In timer mode, the register is incremented every machine cycle, meaning that it counts up after every 12 periods of the MPU clock signal.
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73S1215F Data Sheet DS_1215F_003 Table 42: Timers/Counters Mode Description M1 M0 Mode Function 0 0 Mode 0 13-bit Counter/Timer. 0 1 Mode 1 16-bit Counter/Timer. 1 0 Mode 2 8-bit auto-reload Counter/Timer. 1 1 Mode 3 If Timer 1 M1 and M0 bits are set to '1', Timer 1 stops. If Timer 0 M1 and M0 bits are set to '1', Timer 0 acts as two independent 8-bit Timer/Counters. Mode 0 Putting either timer/counter into mode 0 configures it as an 8-bit timer/counter with a divide-by-32 prescaler.
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DS_1215F_003 73S1215F Data Sheet Timer/Counter Control Register (TCON): 0x88 Å 0x00 Table 43: The TCON Register MSB LSB TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Bit Symbol Function TCON.7 TF1 The Timer 1 overflow flag is set by hardware when Timer 1 overflows. This flag can be cleared by software and is automatically cleared when an interrupt is processed. TCON.6 TR1 Timer 1 Run control bit. If cleared, Timer 1 stops. TCON.5 TF0 Timer 0 overflow flag set by hardware when Timer 0 overflows.
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73S1215F Data Sheet DS_1215F_003 Interrupt Enable 0 Register (IEN0): 0xA8 Å 0x00 Table 44: The IEN0 Register MSB LSB EAL WDT ET2 ES0 ET1 Bit Symbol IEN0.7 EAL EAL = 0 – disable all interrupts. IEN0.6 WDT Watchdog timer refresh flag. EX1 ET0 EX0 Function Set to initiate a refresh of the watchdog timer. Must be set directly before SWDT is set to prevent an unintentional refresh of the watchdog timer. WDT is reset by hardware 12 clock cycles after it has been set. IEN0.5 – IEN0.
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DS_1215F_003 73S1215F Data Sheet Interrupt Priority 0 Register (IP0): 0xA9 Å 0x00 Table 46: The IP0 Register MSB LSB – WDTS IP0.5 IP0.4 IP0.3 IP0.2 IP0.1 IP0.0 Bit Symbol Function IP0.6 WDTS Watchdog timer status flag. Set when the watchdog timer has expired. The internal reset will be generated, but this bit will not be cleared by the reset. This allows the user program to determine if the watchdog timer caused the reset to occur and respond accordingly.
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73S1215F Data Sheet 1.7.7 DS_1215F_003 User (USR) Ports The 73S1215F includes 9 pins of general purpose digital I/O (GPIO). On reset or power-up, all USR pins are inputs until they are configured for the desired direction. The pins are configured and controlled by the USR and UDIR SFRs. Each pin declared as USR can be configured independently as an input or output with the bits of the UDIRn registers. Table 48 lists the direction registers and configurability associated with each group of USR pins.
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DS_1215F_003 73S1215F Data Sheet External Interrupt Control Register (USRIntCtl1) : 0xFF90 Å 0x00 Table 51: The USRIntCtl1 Register MSB – LSB U1IS.6 U1IS.5 U1IS.4 – U0IS.2 U0IS.1 U0IS.0 External Interrupt Control Register (USRIntCtl2) : 0xFF91 Å 0x00 Table 52: The USRIntCtl2 Register MSB – LSB U3IS.6 U3IS.5 U3IS.4 – U2IS.2 U2IS.1 U2IS.0 External Interrupt Control Register (USRIntCtl3) : 0xFF92 Å 0x00 Table 53: The USRIntCtl3 Register MSB – LSB U5IS.6 U5IS.5 U5IS.4 – U4IS.2 U4IS.
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73S1215F Data Sheet 1.7.8 DS_1215F_003 Real-Time Clock with Hardware Watchdog (RTC) R/W BUS Figure 9 shows the block diagram of the Real Time Clock. The RTC block uses the 32768Hz oscillator signal and divider logic to produce 0.5-second time marks. The time marks are used to create interrupts at intervals from 0.5 seconds to 8 seconds as selected by RTC Interval (RTCINV(2:0)). The 32768Hz oscillator can be disabled but is intended to operate at all times and in all power consumption modes.
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DS_1215F_003 73S1215F Data Sheet A 32-bit RTC counter is clocked by a selectable clock (1/2, 1, 2 second) to measure time. A trimming function is provided such that a trim value is accumulated in a 24-bit accumulator at the same rate as the RTC counter. The trim value is sign magnitude number. When the accumulator reaches overflow, it will advance the counter one additional count if the trim value is positive, or prevent the counter from advancing one count if the trim value is negative.
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73S1215F Data Sheet DS_1215F_003 There are 3 sets of registers to load the RTC 24-bit accumulator, 32-bit counter and 23-bit trim registers. The registers are loaded when the RTCLD bit is set in RTCCtl.
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DS_1215F_003 1.7.9 73S1215F Data Sheet Analog Voltage Comparator The 73S1215F includes a programmable comparator that is connected to the ANA_IN pin. The comparator can be configured to trigger an interrupt if the input voltage rises above or falls below a selectable threshold voltage. The comparator control register should not be modified when the analog interrupt (ANAIEN bit in the INT6Ctl register) is enabled to guard against any false interrupt that might be generated when modifying the threshold.
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73S1215F Data Sheet DS_1215F_003 External Interrupt Control Register (INT6Ctl): 0xFF95 Å 0x00 Table 61: The INT6Ctl Register MSB LSB – – VFTIEN VFTINT I2CIEN I2CINT ANIEN ANINT Bit Symbol INT6Ctl.7 – INT6Ctl.6 – INT6Ctl.5 VFTIEN VDD fault interrupt enable. INT6Ctl.4 VFTINT VDD fault interrupt flag. INT6Ctl.3 I2CIEN I2C interrupt enabled. INT6Ctl.2 I2CINT I2C interrupt flag. INT6Ctl.1 ANIEN If ANIEN = 1 Analog Compare event interrupt is enabled.
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DS_1215F_003 73S1215F Data Sheet 1.7.10 LED Drivers The 73S1215F F provides four dedicated output pins for driving LEDs. The LED driver pins can be configured as current sources that will pull to ground to drive LEDs that are connected to VDD without the need for external current limiting resistors. These pins may be used as general purpose outputs with the programmed pull-down current and a strong (CMOS) pull-up, if enabled.
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73S1215F Data Sheet DS_1215F_003 1.7.11 I2C Master Interface The 73S1215F includes a dedicated fast mode, 400kHz I2C Master interface. The I2C interface can read or write 1 or 2 bytes of data per data transfer frame.
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DS_1215F_003 73S1215F Data Sheet Figure 10 shows the timing of the I2C write mode.
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73S1215F Data Sheet DS_1215F_003 Figure 11 shows the timing of the I2C read mode.
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DS_1215F_003 73S1215F Data Sheet Device Address Register (DAR): 0xFF80 Å 0x00 Table 63: The DAR Register MSB LSB DVADR.6 Bit DVADR.5 DVADR.4 DVADR.3 DVADR.2 Symbol DVADR.1 DVADR.0 I2CRW Function DAR.7 DAR.6 DAR.5 DAR.4 DAR.3 DVADR [0:6] Slave device address. I2CRW If set = 0, the transaction is a write operation. If set = 1, read. DAR.2 DAR.1 DAR.0 I2C Write Data Register (WDR): 0XFF81 Å 0x00 Table 64: The WDR Register MSB WDR.7 Bit LSB WDR.6 WDR.5 WDR.4 WDR.3 WDR.2 WDR.1 WDR.
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73S1215F Data Sheet DS_1215F_003 I2C Secondary Write Data Register (SWDR): 0XFF82 Å 0x00 Table 65: The SWDR Register MSB SWDR.7 LSB SWDR.6 SWDR.5 SWDR.4 SWDR.3 Bit SWDR.2 SWDR.1 SWDR.0 Function SWDR.7 SWDR.6 SWDR.5 SWDR.4 SWDR.3 Second Data byte to be written to the I2C slave device if bit 0 (I2CLEN) of the Control and Status register (CSR) is set = 1. SWDR.2 SWDR.1 SWDR.0 I2C Read Data Register (RDR): 0XFF83 Å 0x00 Table 66: The RDR Register MSB RDR.7 LSB RDR.6 RDR.5 RDR.4 Bit RDR.
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DS_1215F_003 73S1215F Data Sheet I2C Secondary Read Data Register (SRDR): 0XFF84 Å 0x00 Table 67: The SRDR Register MSB LSB SRDR.7 SRDR.6 SRDR.5 SRDR.4 Bit SRDR.3 SRDR.2 SRDR.1 SRDR.0 Function SRDR.7 SRDR.6 SRDR.5 SRDR.4 Second Data byte to be read from the I2C slave device if bit 0 (I2CLEN) of the Control and Status register (CSR) is set = 1. SRDR.3 SRDR.2 SRDR.1 SRDR.
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73S1215F Data Sheet DS_1215F_003 External Interrupt Control Register (INT6Ctl): 0xFF95 Å 0x00 Table 69: The INT6Ctl Register MSB LSB – – VFTIEN VFTINT I2CIEN I2CINT ANIEN ANINT Bit Symbol INT6Ctl.7 – INT6Ctl.6 – INT6Ctl.5 VFTIEN VDD fault interrupt enable. INT6Ctl.4 VFTINT VDD fault interrupt flag. INT6Ctl.3 I2CIEN When set = 1, the I2C interrupt is enabled. INT6Ctl.2 I2CINT When set =1, the I2C transaction has completed. Cleared upon the start of a subsequent I2C transaction.
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DS_1215F_003 73S1215F Data Sheet 1.7.12 Keypad Interface The 73S1215F supports a 30-button (6 row x 5 column) keypad (SPST Mechanical Contact Switches) interface using 11 dedicated I/O pins. Figure 12 shows a simplified block diagram of the keypad interface.
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73S1215F Data Sheet DS_1215F_003 32768Hz crystal or the 12MHz crystal. The selection of the clock source is made external to this block, by setting bit 3 – 32KBEN – in the MCLKCtl register (see the oscillator and clock generation section). Disabling the 32kHz oscillator will source the 1kHz clock from the 12MHz main oscillator and divide it down. Setting bit 6 – KBEN – in the MCLKCtl register will enable keypad scanning and debouncing. The keypad size can be adjusted within the KSIZE register.
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DS_1215F_003 73S1215F Data Sheet KSTAT Register: Enable HW Scanning Enable Keypad Interrupt Keypad Initialization All Column Outputs = 0 Any Row Input = 0 ? No Yes No Deboucing Timer KSCAN Register: Debouncing Time Any Row Input still = 0 ? KSIZE Register: Keypad Size Definition KORDERL / H Registers: Column Scan Order Keypad Scanning KSCAN Register: Scanning Rate How Many keys have been detected? More than 1 key 0 key 1 key Download of the key row and column values in KROW and KCOL registers K
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73S1215F Data Sheet DS_1215F_003 Keypad Column Register (KCOL): 0xD1 Å 0x1F This register contains the value of the column of a key detected as valid by the hardware. In bypass mode, this register firmware writes directly this register to carry out manual scanning. Table 70: The KCOL Register MSB LSB – – Bit Symbol KCOL.7 – KCOL.6 – KCOL.5 – KCOL.4 COL.4 KCOL.3 COL.3 KCOL.2 COL.2 KCOL.1 COL.1 KCOL.0 COL.0 – COL.4 COL.3 COL.2 COL.1 COL.
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DS_1215F_003 73S1215F Data Sheet Keypad Scan Time Register (KSCAN): 0xD3 Å 0x00 This register contains the values of scanning time and debouncing time. Table 72: The KSCAN Register MSB LSB DBTIME.5 DBTIME.4 Bit Symbol KSCAN.7 DBTIME.5 KSCAN.6 DBTIME.4 KSCAN.5 DBTIME.3 KSCAN.4 DBTIME.2 KSCAN.3 DBTIME.1 KSCAN.2 DBTIME.0 KSCAN.1 SCTIME.1 KSCAN.0 SCTIME.0 DBTIME.3 DBTIME.2 DBTIME.1 DBTIME.0 SCTIME.1 SCTIME.0 Function De-bounce time in 4ms increments.
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73S1215F Data Sheet DS_1215F_003 Keypad Scan Time Register (KSIZE): 0xD5 Å 0x00 This register is not applicable when HWSCEN is not set. Unused row inputs should be connected to VDD. Table 74: The KSIZE Register MSB LSB – – ROWSIZ.2 Bit Symbol KSIZE.7 – KSIZE.6 – KSIZE.5 ROWSIZ.2 KSIZE.4 ROWSIZ.1 KSIZE.3 ROWSIZ.0 KSIZE.2 COLSIZ.2 KSIZE.1 COLSIZ.1 KSIZE.0 COLSIZ.0 ROWSIZ.1 ROWSIZ.0 COLSIZ.2 COLSIZ.1 COLSIZ.0 Function Defines the number of rows in the keypad.
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DS_1215F_003 73S1215F Data Sheet Keypad Column MS Scan Order Register (KORDERH): 0xD7 Å 0x00 Table 76: The KORDERH Register MSB LSB – 5COL.2 Bit Symbol KORDERH.7 – KORDERH.6 5COL.2 KORDERH.5 5COL.1 KORDERH.4 5COL.0 KORDERH.3 4COL.2 KORDERH.2 4COL.1 KORDERH.1 4COL.0 KORDERH.0 3COL.2 5COL.1 5COL.0 4COL.2 4COL.1 4COL.0 3COL.2 Function Column to scan 5th. Column to scan 4th. Column to scan 3rd (msb).
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73S1215F Data Sheet DS_1215F_003 1.7.13 Emulator Port The emulator port, consisting of the pins E_RST, E_TCLK and E_RXTX, provides control of the MPU through an external in-circuit emulator. The E_TBUS[3:0] pins, together with the E_ISYNC/BRKRQ, add trace capability to the emulator. The emulator port is compatible with the ADM51 emulators manufactured by Signum Systems.
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DS_1215F_003 73S1215F Data Sheet The USB interface includes a Serial Interface Engine (SIE) that handles NRZI encoding/decoding, bit stuffing / unstuffing, and CRC generation/checking. It also generates headers for packets to be transmitted and decodes the headers of received packets. An analog transceiver interfaces with the external USB bus. The USB interface hardware performs error checking and removes the USB protocol fields from the incoming messages before passing the data to the firmware.
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73S1215F Data Sheet DS_1215F_003 1.7.14.1 USB Interface Implementation The 73S1215F Application Programming Interface includes some dedicated software commands to configure the USB interface, to get a status of each USB Endpoint, to stall / unstall portions of the USB, and to send / receive data to / from each endpoint. USB API entirely manages the USB circuitry, the USB registers and the FIFOs. Use of those commands facilitates USB implementation, without dealing with low-level programming.
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DS_1215F_003 73S1215F Data Sheet Clock Control Register (CKCON): 0x8E Å 0x01 Table 79: The CKCON Register MSB LSB – – Bit Symbol CKCON.7 – CKCON.6 – CKCON.5 – CKCON.4 – CKCON.3 – CKCON.2 CKWT.2 CKCON.1 CKWT.1 CKCON.0 CKWT.0 Rev. 1.4 – – – CKWT.2 CKWT.1 CKWT.0 Function These three bits determine the number of wait states (machine cycles) to insert when accessing the USB SFRs: 000 = 0 (not to be used). 001 = 1 wait state. Use when MPU clock is <12MHz. 010 = 2 wait states.
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73S1215F Data Sheet DS_1215F_003 1.7.15 Smart Card Interface Function The 73S1215F integrates one ISO-7816 (T=0, T=1) UART, one complete ICC electrical interface as well as an external smart card interface to allow multiple iple smart cards to be connected using the Teridian 8010 family of interface devices. Figure 15 shows the simplified block diagram of the card circuitry (UART + interfaces), with detail of dedicated XRAM registers.
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DS_1215F_003 73S1215F Data Sheet on a card insertion / removal to allow power saving modes. Card insertion / removal is generated from the respective card switch detection inputs (whose polarity is programmable). The built-in ICC Interface has a low dropout regulator (VCC generator) capable of driving 1.8V, 3.0V and 5.0V smart cards in accordance with the ISO 7816-3 and EMV4.0 standards. This converter requires a separate 5.0V input supply source designated as VPC.
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73S1215F Data Sheet DS_1215F_003 1.7.15.1 ISO 7816 UART An embedded ISO 7816 (hardware) UART is provided to control communications between a smart card and the 73S1215F MPU. The UART can be shared between the one built-in ICC interface and the external ICC interface. Selection of the desired interface is made by register SCSel. Control of the external interface is handled by the I2C interface for any external 8010 devices.
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DS_1215F_003 73S1215F Data Sheet Smart card RST, I/O and CLK, C4, C8 shall be low before the end of the deactivation sequence. Figure 18 shows the timing for a deactivation sequence. SELSC bits VCCSEL bits VCC VCCOK bit t4 RSTCRD bit See Note RST CLK ATR starts IO t1 t2 t3 t4 t5 tto t1: SELSC.1 bit set (selects internal ICC interface) and a non-zero value in VCCSEL bits (calling for a value of Vcc of 1.8, 3.0, or 5.0 volts) will begin the activation sequence.
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73S1215F Data Sheet Firmware sets VCCSEL to 00 DS_1215F_003 t5 t5 delay or Card Event IO RST CLK CMDVCCnB VCC t3 t1 t2 t4 t1: Time after either a “card event” occurs or firmware sets the VCCSela and VCCSelb bits to 0 (see t5, VCCOff_tmr) occurs until RST is asserted low. t2: Time after RST goes low until CLK stops. t3: Time after CLK stops until IO goes low. t4: Time after IO goes low until VCC is powered down. t5: Delayed VCC off time (in ETUs per VCCOff_tmr bits).
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DS_1215F_003 73S1215F Data Sheet FDReg(3:0) FDReg(7:4) FI Decoder F/D Register Pre-Scaler 6 bits ETUCLK EDGE ETU Divider 12 bits 7.38M 1/13 9926 CENTER 1/744 SCSel(3:2) SCCLK(5:0) MSCLK SCSCLK(5:0) 7.38M DIV by 2 SYNC 3.69M CLK MCLK = 96MHz PLL Pre-Scaler 6 bits MSCLKE 7.38M 1/13 DIV by 2 3.69M SCLK Defaults in Italics Figure 19: Smart Card CLK and ETU Generation There are two, two-byte FIFOs that are used to buffer transmit and receive data.
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73S1215F Data Sheet DS_1215F_003 T = 0 Mode > EGT CHAR 1 CHAR 2 < WWT WWT is set by the value in the BWT registers. T = 1 Mode TRANSMISSION RECEPTION (By seting Last_TXByte and TX/RXB=0 during CHAR N, RX mode will start after last TX byte) BLOCK1 CHAR 1 CHAR 2 CHAR N BGT(4:0) BLOCK2 CHAR N+1 CHAR N+2 CHAR N+3 TX > BWT EGT < CWT ATR Timing Parameters CHAR 1 CHAR 2 CHAR N IO TSTO(7:0) ATRTO(15:0) RST IWT(15:0) RLen(7:0) VCC_OK Figure 20: Guard, Block, Wait and ATR Time Definitions 1.7.
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DS_1215F_003 73S1215F Data Sheet Special Notes Regarding Synchronous Mode Operation When the SCISYN or SCESNC bits (SPrtcol, bit 7, bit 5, respectively) are set, the selected smart card interface operates in synchronous mode and there are changes in the definition and behavior of pertinent register bits and associated circuitry. The following requirements are to be noted: 1. The source for the smart card clock (CLK or SCLK) is the ETU counter.
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73S1215F Data Sheet DS_1215F_003 VCCSEL bits VCC VCCOK RSTCRD RST t3 CLK IO t4 t1 t2 tto t1: The time from setting VCCSEL bits until VCCOK = 1. tto: The time from setting VCCSEL bits until VCCTMR times out. At t1 (if RDYST = 1) or tto (if RDYST = 0), activation starts. It is suggested to have RDYST = 0 and use the VCCTMR interrupt to let MPU know when sequence is starting. t2: time from start of activation (no external indication) until IO goes into reception mode (= 1).
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DS_1215F_003 73S1215F Data Sheet START Bit CLK IO Data from Card -end of ATR RLength Count MAX RLength Count - was set for length of ATR 1 RLength Interrupt Data from TX FIFO 6 RLen=0 5 Rlen=1 2 CLK Stop 3 CLK Stop Level 7 IO Bit IODir Bit 6 TX/RX Mode Bit TX = '1' 4 1. Interrupt generated when Rlength counter is MAX. 2. Read and clear Interrupt. 3. Set CLK Stop and CLK Stop level high in Interrupt routine. 4. Set TX/RX Bit to TX mode. 5. Reload Rlength Counter. 6.
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73S1215F Data Sheet DS_1215F_003 CLK IO RLength Count RLength = 9 Data from Card (Bit 8) Protection Bit (Bit 9) RLength Count MAX Rlen=9 Rlen=8 Data from Card (Bit 1) Rlen=0 Rlen =1 RLength Interrupt RX FIFO (Data from Card is ready for CPU read) RX data Protection Bit Data (Bit 9) Protection Bit is ready for CPU read TX/RX Mode Bit TX = '1' 1._ Interrupt generated when Rlength counter is Max 2._ Read and clear Interrupt 3.
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DS_1215F_003 73S1215F Data Sheet Smart Card SFRs Smart Card Select Register (SCSel): 0xFE00 Å 0x00 Table 80: The SCSel Register MSB – LSB – – – SELSC.1 SELSC.0 BYPASS – The smart card select register is used to determine which smart card interface is using the ISO UART. The internal Smart Card has integrated 7816-3 compliant sequencer circuitry to drive an external smart card interface.
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73S1215F Data Sheet DS_1215F_003 Smart Card Interrupt Register (SCInt): 0xFE01 Å 0x00 When the smart card interrupt is asserted, the firmware can read this register to determine the actual cause of the interrupt. The bits are cleared when this register is read. Each interrupt can be disabled by the Smart Card Interrupt Enable register. Error processing must be handled by the firmware. This register relates to the interface that is active – see the SCSel register.
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DS_1215F_003 73S1215F Data Sheet Smart Card Interrupt Enable Register (SCIE): 0xFE02 Å 0x00 When set to a 1, the respective condition can cause a smart card interrupt. When set to a 0, the respective condition cannot cause an interrupt. When disabled, the respective bit in the Smart Card Interrupt register can still be set, but it will not interrupt the MPU. Table 83: The SCIE Register MSB LSB WTOIEN CDEVEN VTMREN RXDAEN TXEVEN TXSNTEN TXEREN RXEREN Bit Symbol Function SCIE.
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73S1215F Data Sheet DS_1215F_003 Smart Card VCC Control/Status Register (VccCtl): 0xFE03 Å 0x00 This register is used to control the power up and power down of the integrated smart card interface. It is used to determine whether to apply 5V, 3V, or 1.8V to the smart card. Perform the voltage selection with one write operation, setting both VCCSEL.1 and VCCSEL.0 bits simultaneously. The VDDFLT bit (if enabled) will provide an emergency deactivation of the internal smart card slot.
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DS_1215F_003 73S1215F Data Sheet VCC Stable Timer Register (VccTmr): 0xFE04 Å 0x0F A programmable timer is provided to set the time from activation start (setting the VCCSEL.1 and VCCSEL.0 bits to non-zero) to when VCC_OK is evaluated. VCC_OK must be true at the end of this timers programmed interval (tto in Figure 17) in order for the activation sequence to continue.
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73S1215F Data Sheet DS_1215F_003 Card Status/Control Register (CRDCtl): 0xFE05 Å 0x00 This register is used to configure the card detect pin (DETCARD) and monitor card detect status. This register be written to properly configure Debounce, Detect_Polarity (= 0 or = 1), and the pull-up/down enable before setting CDETEN. The card detect logic is functional even without smart card logic clock. When the PWRDN bit is set = 1, no debounce is provided but card presence is operable.
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DS_1215F_003 73S1215F Data Sheet TX Control/Status Register (STXCtl): 0xFE06 Å 0x00 This register is used to control transmission of data to the smart card. Some control and some status bits are in this register. Table 86: The STXCtl Register MSB LSB I2CMODE Bit STXCtl.
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73S1215F Data Sheet DS_1215F_003 STX Data Register (STXData): 0xFE07 Å 0x00 Table 87: The STXData Register MSB LSB STXDAT.7 STXDAT.6 STXDAT.5 STXDAT.4 Bit STXDAT.3 STXDAT.2 STXDAT.1 STXDAT.0 Function STXData.7 STXData.6 STXData.5 STXData.4 STXData.3 STXData.2 Data to be transmitted to smart card. Gets stored in the TX FIFO and then extracted by the hardware and sent to the selected smart card. When the MPU reads this register, the byte pointer is changed to effectively “read out” the data.
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DS_1215F_003 73S1215F Data Sheet SRX Data Register (SRXData): 0xFE09 Å 0x00 Table 89: The SRXData Register MSB LSB SRXDAT.7 SRXDAT.6 SRXDAT.5 SRXDAT.4 SRXDAT.3 SRXDAT.2 SRXDAT.1 SRXDAT.0 Bit Function SRXData.7 SRXData.6 SRXData.5 SRXData.4 SRXData.3 (Read only) Data received from the smart card. Data received from the smart card gets stored in a FIFO that is read by the firmware. SRXData.2 SRXData.1 SRXData.0 Rev. 1.
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73S1215F Data Sheet DS_1215F_003 Smart Card Control Register (SCCtl): 0xFE0A Å 0x21 This register is used to monitor reception of data from the smart card. Table 90: The SCCtl Register MSB LSB RSTCRD Bit IO IOD C8 C4 CLKLVL CLKOFF Symbol Function SCCtl.7 RSTCRD 1 = Asserts the RST (set RST = 0) to the smart card interface, 0 = Deassert the RST (set RST = 1) to the smart card interface. Can be used to extend RST to the smart card. Refer to the RLength register description.
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DS_1215F_003 73S1215F Data Sheet External Smart Card Control Register (SCECtl): 0xFE0B Å 0x00 Used to directly set and sample signals of External Smart Card interface. There are three modes of asynchronous operation, an “automatic sequence” mode, and bypass mode. Clock stop per the ISO 7816-3 interface is also supported but firmware must handle the protocol for SIO and SCLK for I2C clock stop and start. Control for Reset (to make RST signal), activation control, voltage select, etc.
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73S1215F Data Sheet DS_1215F_003 C4/C8 Data Direction Register (SCDIR): 0xFE0C Å 0x00 This register determines the direction of the internal interface C4/C8 lines. After reset, all signals are tri-stated. Table 92: The SCDIR Register MSB LSB – – – – C8D C4D Bit Symbol SCDIR.7 – SCDIR.6 – SCDIR.5 – SCDIR.4 – SCDIR.3 C8D 1 = input, 0 = output. Smart Card C8 direction. SCDIR.2 C4D 1 = input, 0 = output. Smart Card C4 direction. SCDIR.1 – SCDIR.0 – 98 – – Function Rev. 1.
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DS_1215F_003 73S1215F Data Sheet Protocol Mode Register (SPrtcol): 0xFE0D Å 0x03 This register determines the protocol to be use when communicating with the selected smart card. This register should be updated as required when switching between smart card interfaces. Table 93: The SPrtcol Register MSB LSB SCISYN Bit SPrtcol.7 MOD9/8B SCESYN 0 TMODE CRCEN CRCMS RCVATR Symbol Function SCISYN Smart Card Internal Synchronous mode – Configures internal smart card interface for synchronous mode.
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73S1215F Data Sheet DS_1215F_003 SC Clock Configuration Register (SCCLK): 0xFE0F Å 0x0C This register controls the internal smart card (CLK) clock generation. Table 94: The SCCLK Register MSB LSB – – ICLKFS.5 ICLKFS.4 ICLKFS.3 ICLKFS.2 ICLKFS.1 ICLKFS.0 Bit Symbol Function SCCLK.7 – SCCLK.6 – SCCLK.5 ICLKFS.5 SCCLK.4 ICLKFS.4 SCCLK.3 ICLKFS.3 SCCLK.2 ICLKFS.2 SCCLK.1 ICLKFS.1 SCCLK.0 ICLKFS.
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DS_1215F_003 73S1215F Data Sheet Parity Control Register (SParCtl): 0xFE11 Å 0x00 This register provides the ability to configure the parity circuitry on the smart card interface. The settings apply to both integrated smart card interfaces. Table 96: The SParCtl Register MSB – LSB DISPAR BRKGEN BRKDET RETRAN DISCRX INSPE FORCPE Bit Symbol SParCtl.7 – SParCtl.6 DISPAR Disable Parity Check – 1 = disabled, 0 = enabled.
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73S1215F Data Sheet DS_1215F_003 Byte Control Register (SByteCtl): 0xFE12 Å 0x2C This register controls the processing of characters and the detection of the TS byte. When receiving, a Break is asserted at 10.5 ETU after the beginning of the start bit. Break from the card is sampled at 11 ETU. Table 97: The SByteCtl Register MSB – LSB DETTS DIRTS BRKDUR.1 BRKDUR.0 – – – Table 98: The SByteCtl Bit Functions Bit Symbol SByteCtl.
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DS_1215F_003 73S1215F Data Sheet FD Control Register (FDReg): 0xFE13 Å 0x11 This register uses the transmission factors F and D to set the ETU (baud) rate. The values in this register are mapped to the ISO 7816 conversion factors as described below. The CLK signal for each interface is created by dividing a high-frequency, intermediate signal (MSCLK) by 2. The ETU baud rate is created by dividing MSCLK by 2 times the Fi/Di ratio specified by the codes below.
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73S1215F Data Sheet DS_1215F_003 Table 101: Divider Values for the ETU Clock Di code Fi code F→ D↓ 0000 372 0001 372 0010 558 0011 744 0100 1116 0101 1488 0001 0010 0011 0100 1000 0101 1001 0110 1 2 4 8 12 16 20 32 744 372 186 93 62 47 37 23 744 372 186 93 62 47 37 23 1116 558 279 138 93 70 56 35 1488 744 372 186 124 93 74 47 2232 1116 558 279 186 140 112 70 2976 1488 744 372 248 186 149 93 Di code Fi code F→ D↓ 0110 1860 1001 512 1010 768 1011 1024 1100 1536 1101 2048 0001 0010 00
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DS_1215F_003 73S1215F Data Sheet CRC MS Value Registers (CRCMsB): 0xFE14 Å 0xFF, (CRCLsB): 0xFE15 Å 0xFF Table 103: The CRCMsB Register MSB CRC.15 LSB CRC.14 CRC.13 CRC.12 CRC.11 CRC.10 CRC.9 CRC.8 Table 104: The CRCLsB Register MSB CRC.7 LSB CRC.6 CRC.5 CRC.4 CRC.3 CRC.2 CRC.1 CRC.0 The 16-bit CRC value forms the TX CRC word in TX mode (write value) and the RX CRC in RX mode (read value).
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73S1215F Data Sheet DS_1215F_003 Block Guard Time Register (BGT): 0xFE16 Å 0x10 This register contains the Extra Guard Time Value (EGT) most-significant bit. The Extra Guard Time indicates the minimum time between the leading edges of the start bit of consecutive characters. The delay is depends on the T=0/T=1 mode. Used in transmit mode. This register also contains the Block Guard Time (BGT) value.
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DS_1215F_003 73S1215F Data Sheet Block Wait Time Registers (BWTB0): 0xFE1B Å 0x00, (BWTB1): 0xFE1A Å 0x00, (BWTB2): 0xFE19 Å 0x00, (BWTB3): 0xFE18 Å 0x00 Table 107: The BWTB0 Register MSB LSB BWT.7 BWT.6 BWT.5 BWT.4 BWT.3 BWT.1 BWT.2 BWT.0 Table 108: The BWTB1 Register MSB LSB BWT.15 BWT.14 BWT.13 BWT.12 BWT.11 BWT.10 BWT.9 BWT.8 Table 109: The BWTB2 Register MSB LSB BWT.23 BWT.22 BWT.21 BWT.20 BWT.19 BWT.18 BWT.17 BWT.
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73S1215F Data Sheet DS_1215F_003 ATR Timeout Registers (ATRLsB): 0xFE20 Å 0x00, (ATRMsB): 0xFE1F Å 0x00 Table 113: The ATRLsB Register MSB LSB ATRTO.7 ATRTO.6 ATRTO.5 ATRTO.4 ATRTO.3 ATRTO.1 ATRTO.2 ATRTO.0 Table 114: The ATRMsB Register MSB LSB ATRTO.15 ATRTO.14 ATRTO.13 ATRTO.12 ATRTO.11 ATRTO.10 ATRTO.9 ATRTO.8 These registers (ATRLsB and ATRLsB) form the ATR timeout (ATRTO [15:0]) parameter.
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DS_1215F_003 73S1215F Data Sheet Shaded locations indicate functions that are not provided in sync mode.
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73S1215F Data Sheet DS_1215F_003 1.7.16 VDD Fault Detect Function The 73S1215F contains a circuit to detect a low-voltage condition on the supply voltage VDD. If enabled, it will deactivate the active internal smart card interface when VDD falls below the VDD Fault threshold. The register configures the VDD Fault threshold for the nominal default of 2.3V* or a user selectable threshold.
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DS_1215F_003 73S1215F Data Sheet 2 Typical Application Schematic OPTIONAL LCD DISPLAY SYSTEM 16 CHARACTER BY 2 LINES U5 J6 6 C17 0.1uF R5 NC DB7 15 DB6 14 13 USR2 DB5 12 USR1 DB3 DB2 DB1 DB0 E R/W* RS VO VDD GND DB4 11 10 9 8 7 USR0 C24 C25 22pF 22pF 22pF 22pF C29 + C30 1uF 0.1uF D7 LED3 D6 LED1 D5 LED2 D4 LED0 RV1 10K 2 USR3 32.768kHz C23 200k USB_CONN_4 6 12.
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73S1215F Data Sheet DS_1215F_003 3 Electrical Specification 3.1 Absolute Maximum Ratings Operation outside these rating limits may cause permanent damage to the device. The smart card interface pins are protected against short circuits to VCC, ground, and each other. Parameter Rating DC Supply voltage, VDD -0.5 to 4.0 VDC Supply Voltage VPC -0.5 to 6.5 VDC Storage Temperature -60 to 150°C Pin Voltage (except card interface) -0.3 to (VDD+0.5) VDC Pin Voltage (card interface) -0.3 to (VCC+0.
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DS_1215F_003 73S1215F Data Sheet 3.3 Digital IO Characteristics These requirements pertain to digital I/O pin types with consideration of the specific pin function and configuration. The LED(3:0) pins have pull-ups that may be enabled. The Row pins have 100KΩ pullups. Symbol Parameter Conditions Min. Voh Output level, high Ioh =-2mA Vol Output level, low Vih Typ. Max. Unit 0.8 *VDD VDD V Iol=2mA 0 0.3 V Input voltage, high 2.7v < VDD <3.6v 1.8 VDD+0.3 V Vil Input voltage, low 2.
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73S1215F Data Sheet DS_1215F_003 3.4 Oscillator Interface Requirements Symbol Parameter Condition Min Typ. Max Unit Low-Power Oscillator Requirements. No External Load Beside The Crystal And Capacitor Is Permitted On Xout32. Pxtal IIL Power In Crystal Input Leakage Current GND < Vin < VDD -5 1 Μw 5 Μa High-Frequency Oscillator (Xin) Parameters. XIN Is Used As Input For External Clock For Test Purposes Only. A Resistor Connecting X12in To X12out Is Required, Value = 1MΩ.
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DS_1215F_003 73S1215F Data Sheet 3.6 USB Interface Requirements Parameter Condition Min Typ. Max Unit Receiver Parameters Differential input sensitivity VDI |(DP)-(DM)| 0.2 V Differential common mode range VCM Includes VDI range 0.8 2.5 V Single ended receiver threshold VSE 0.8 2.0 V 0.3 V Transmitter Levels Low Level Output Voltage VOL USBCon = 1 (DP pullup enabled) High Level Output Voltage VOH 15KΩ resistor to ground VDD – 0.
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73S1215F Data Sheet DS_1215F_003 Parameter Condition Min Typ. Max Unit CL = 50pf, series 24Ω, 1% source termination resistor included Rise Time USBTR 10% to 90% 4 20 ns Fall Time USBTF 90% to 10% 4 20 ns Rise/fall time matching TRFM (USBTR/USBTF) 90 111.11 % Output signal crossover voltage VCRS Includes VDI range 1.3 2.0 V Source Jitter to Next Transition TDJ1 Measured as in Figure 7-49 of USB 2.0 Spec -3.5 3.
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DS_1215F_003 73S1215F Data Sheet 3.7 Smart Card Interface Requirements Symbol Parameter Condition Min Typ. Max Unit Card Power Supply (VCC) Regulator General conditions, -40°C < T < 85°C, 4.75V < VPC < 6.0V, 2.7V < VDD < 3.6V VCC Card supply Voltage including ripple and noise Inactive mode -0.1 0.1 V Inactive mode, ICC = 1mA -0.1 0.4 V Active mode; ICC <65mA; 5V 4.65 5.25 V Active mode; ICC <65mA; 5V, NDS condition 4.75 5.25 V Active mode; ICC < 65mA; 3V 2.85 3.
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73S1215F Data Sheet Symbol Parameter DS_1215F_003 Condition Min Typ. Max Unit Interface Requirements – Data Signals: I/O, AUX1 and AUX2 VOH Output level, high (I/O, AUX1, AUX2) IOH =0 0.9 * VCC VCC+0.1 V IOH = -40μA 0.75 VCC VCC+0.1 V VOL Output level, low (I/O, AUX1, AUX2) IOL=1mA 0.15 *VCC V VIH Input level, high (I/O, AUX1, AUX2) 0.6 * VCC VCC+0.30 V VIL Input level, low (I/O, AUX1, AUX2) -0.15 0.2 * VCC V VINACT Output voltage when outside of session IOL = 0 0.
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DS_1215F_003 3.7.1 73S1215F Data Sheet DC Characteristics Symbol IDD IPC IPCOFF Parameter Supply Current Supply Current VPC supply current when VCC = 0 Condition Min Typ. Max Unit CPU clock @ 24MHz 30 35 mA CPU clock @ 12MHz 22 25.5 mA CPU clock @ 6MHz 16 19.5 mA CPU clock @ 3.
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73S1215F Data Sheet DS_1215F_003 4 Equivalent Circuits VDD X12LIN X12OUT ESD ESD ENABLE TTL To circuit Figure 27: 12 MHz Oscillator Circuit VDD ENABLEb X32OUT >1MEG X32LIN ESD ESD TTL To circuit Figure 28: 32kHz Oscillator Circuit 120 Rev. 1.
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DS_1215F_003 73S1215F Data Sheet VDD STRONG PFET Output Disable PIN ESD Data From circuit TTL To circuit STRONG NFET Figure 29: Digital I/O Circuit VDD Output Disable STRONG PFET PIN Data From circuit ESD STRONG NFET Figure 30: Digital Output Circuit Rev. 1.
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73S1215F Data Sheet DS_1215F_003 VDD VERY WEAK PFET Pull-up Disable STRONG PFET Output Disable PIN ESD Data From circuit STRONG NFET TTL To circuit Figure 31: Digital I/O with Pull Up Circuit VDD STRONG PFET Output Disable PIN ESD Data From circuit Pull-down Enable TTL To circuit STRONG NFET VERY WEAK NFET Figure 32: Digital I/O with Pull-Down Circuit 122 Rev. 1.
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DS_1215F_003 73S1215F Data Sheet PIN TTL To circuit ESD Figure 33: Digital Input Circuit VDD Pull-up Disable STRONG PFET Output Disable 100k OHM PIN ESD Data From circuit TTL To circuit STRONG NFET Figure 34: Keypad Row Circuit Rev. 1.
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73S1215F Data Sheet DS_1215F_003 VDD 1200 OHMS MEDIUM PFET Output Disable PIN ESD Data From circuit TTL To circuit STRONG NFET Figure 35: Keypad Column Circuit 124 Rev. 1.
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DS_1215F_003 73S1215F Data Sheet VDD STRONG PFET Pullup Disable PIN ESD Data From circuit STRONG NFET TTL To circuit Current Value Control 0, 2, 4, 10mA Figure 36: LED Circuit This buffer has a special input threshold: Vih>0.7*VDD To Circuit Logic PIN ESD R= 20kΩ Figure 37: Test and Security Pin Circuit Rev. 1.
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73S1215F Data Sheet DS_1215F_003 To Comparator Input PIN ESD Figure 38: Analog Input Circuit VCC STRONG PFET ESD From circuit PIN ESD STRONG NFET Figure 39: Smart Card Output Circuit 126 Rev. 1.
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DS_1215F_003 73S1215F Data Sheet VCC STRONG PFET ESD RL=11K 125ns DELAY IO PIN From circuit To circuit CMOS STRONG NFET ESD Figure 40: Smart Card I/O Circuit VDD ESD Pull-down Enable PIN TTL To circuit VERY WEAK NFET ESD Figure 41: PRES Input Circuit Rev. 1.
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73S1215F Data Sheet DS_1215F_003 VDD VERY WEAK PFET Pull-up Enable ESD PIN TTL To circuit ESD Figure 42: PRES Input Circuit VDD RP_ENb VDD 1500 Ω DP DP_OUT ZOUT= 20Ω DP_IN ESD TTL OUTPUT ENABLEb IN_P RCV_IN DM_IN TTL IN_N VDD DM DM_OUT ZOUT= 20Ω OUTPUT ENABLEb ESD Figure 43: USB Circuit 128 Rev. 1.
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DS_1215F_003 73S1215F Data Sheet 5 Package Pin Designation 5.1 68-pin QFN Pinout X12OUT XI2IN GND X32IN X32OUT SDA SCL LED3 LED1 LED2 LED0 11 10 8 6 5 4 3 2 1 7 COL1 COL0 13 9 ANAIN COL2 15 12 COL3 16 14 RXD 17 CAUTION: Use handling procedures necessary for a static sensitive component.
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73S1215F Data Sheet DS_1215F_003 5.2 .2 44-pin QFN Pinout XI2IN GND SDA SCL LED1 LED0 SEC RESET 8 7 6 5 4 3 1 2 X12OUT 9 10 RXD ANA_IN 11 CAUTION: Use handling procedures necessary for a static sensitive component.
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DS_1215F_003 73S1215F Data Sheet 6 Packaging Information 6.1 68-Pin QFN Package Outline Notes: 6.3mm x 6.3mm exposed pad area must remain UNCONNECTED (clear of PCB traces or vias). Controlling dimensions are in mm. 0.65 8.00 7.75 0.85 0.2 0.00/0.05 68 1 2 3 7.75 8.00 TOP VIEW 12° SEATING PLANE 8.00 0.42 0.24/0.60 6.30 6.15/6.45 68 0.00/0.05 1 2 0.45 SIDE VIEW PIN#1 ID R0.20 0.20 0.15/0.25 3 0.42 0.24/0.60 SECTION "C-C" 6.30 6.40 8.00 6.15/6.45 SCALE: NONE C C CL 6.40 0.
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73S1215F Data Sheet 6.2 DS_1215F_003 44-Pin QFN Package Outline Notes: 5.1mm x 5.1mm exposed pad area must remain UNCONNECTED (clear of PCB traces or vias). Controlling dimensions are in mm. 0.65 7.00 6.75 0.85 0.2 0.00/0.05 44 1 2 3 6.75 7.00 TOP VIEW 12° SEATING PLANE 7.00 0.42 0.24/0.60 4.95/5.25 SIDE VIEW PIN#1 ID R0.20 5.10 44 0.00/0.05 1 0.45 0.23 0.18/0.30 2 3 0.42 0.24/0.60 SECTION "C-C" 5.10 5.00 7.00 4.95/5.25 SCALE: NONE C C CL 5.00 0.
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DS_1215F_003 73S1215F Data Sheet 7 Ordering Information Table 119 lists the order numbers and packaging marks used to identify 73S1215F products.
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73S1215F Data Sheet DS_1215F_003 Revision History Revision Date Description 1.1 1.3 2/2/2007 11/6/2007 First publication. On page 2, changed bullet from “ISO-7816 UART 9600 to 115kbps for protocols T=0, T=1” to “ISO-7816 UART for protocols T=0, T=1”. In Table 1, added Equivalent Circuit references. In Table 3 and Table 5, removed the PREBOOT bit description. In Section 1.4, updated program security description to remove pre-boot and 32-cycle references. In Section 1.
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DS_1215F_003 1.4 12/16/2008 73S1215F Data Sheet In Table 1, added more description to the VCC, VPC, VDD, SCL, SDA, PRES, SEC and TEST pins. In Section 1.3.2, changed “FLSH_ERASE” to “ERASE” and “FLSH_PGADR” to “PGADDR”. Added “The PGADDR register denotes the page address for page erase. The page size is 512 (200h) bytes and there are 128 pages within the flash memory.
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73S1215F Data Sheet DS_1215F_003 © 2008 Teridian Semiconductor Corporation. All rights reserved. Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation. Windows is a registered trademark of Microsoft Corporation. Signum Systems is a trademark of Signum Systems Corporation. ExpressCard is a registered trademarks of PCMCIA. All other trademarks are the property of their respective owners.