Datasheet

DS_1215F_003 73S1215F Data Sheet
Rev. 1.4 103
FD Control Register (FDReg): 0xFE13 Å 0x11
This register uses the transmission factors F and D to set the ETU (baud) rate. The values in this register
are mapped to the ISO 7816 conversion factors as described below. The CLK signal for each interface is
created by dividing a high-frequency, intermediate signal (MSCLK) by 2. The ETU baud rate is created
by dividing MSCLK by 2 times the Fi/Di ratio specified by the codes below. For example, if FI = 0001 and
DI = 0001, the ratio of Fi/Di is 372/1. Thus the ETU divider is configured to divide by 2 * 372 = 744. The
maximum supported F/D ratio is 4096.
Table 99: The FDReg Register
MSB LSB
FVAL.3 FVAL.2 FVAL.1 FVAL.0 DVAL.3 DVAL.2 DVAL.1 DVAL.0
Table 100: Divider Ratios Provided by the ETU Counter
FI (code) 0000 0001 0010 0011 0100 0101 0110 0111
Fi (ratio) 372 372 558 744 1116 1488 1860
1860⊕
FCLK max 4 5 6 8 12 16 20
20⊕
FI(code) 1000 1001 1010 1011 1100 1101 1110 1111
Fi(ratio)
512⊕
512 768 1024 1536 2048
2048⊕ 2048⊕
FCLK max
5⊕
5 7.5 10 15 20
20⊕ 20⊕
DI(code) 0000 0001 0010 0011 0100 0101 0110 0111
Di(ratio)
1⊕
1 2 4 8 16 32
32⊕
DI(code) 1000 1001 1010 1011 1100 1101 1110 1111
Di(ratio) 12 20
16⊕ 16⊕ 16⊕ 16⊕ 16⊕ 16⊕
Note: values marked with ⊕ are not included in the ISO definition and arbitrary values have been
assigned.
The values given below are used by the ETU divider to create the ETU clock. The entries that are not
shaded will result in precise CLK/ETU per ISO requirements. Shaded areas are not precise but are
within 1% of the target value.