Datasheet

73S1215F Data Sheet DS_1215F_003
104 Rev. 1.4
Table 101: Divider Values for the ETU Clock
Fi code 0000 0001 0010 0011 0100 0101
Di
code
F→
D↓
372 372 558 744 1116 1488
0001 1 744 744 1116 1488 2232 2976
0010 2 372 372 558 744 1116 1488
0011 4 186 186 279 372 558 744
0100 8 93 93 138 186 279 372
1000 12 62 62 93 124 186 248
0101 16 47 47 70 93 140 186
1001 20 37 37 56 74 112 149
0110 32 23 23 35 47 70 93
Fi code 0110 1001 1010 1011 1100 1101
Di
code
F→
D↓
1860 512 768 1024 1536 2048
0001 1 3720 1024 1536 2048 3072 4096
0010 2 1860 512 768 1024 1536 2048
0011 4 930 256 384 512 768 1024
0100 8 465 128 192 256 384 512
1000 12 310 85 128 171 256 341
0101 16 233 64 96 128 192 256
1001 20 186 51 77 102 154 205
0110 32 116 32 48 64 96 128
Table 102: The FDReg Bit Functions
Bit Symbol Function
FDReg.7 FVAL.3
Refer to Table 101 above. This value is converted per the table to set the
divide ratio used to generate the baud rate (ETU). Default, also used for
ATR, is 0001 (Fi = 372). This value is used by the selected interface.
FDReg.6 FVAL.2
FDReg.5 FVAL.1
FDReg.4 FVAL.0
FDReg.3 DVAL.3
Refer to Table 101 above. This value is used to set the divide ratio used to
generate the smart card CLK. Default, also used for ATR, is 0001 (Di = 1).
FDReg.2 DVAL.2
FDReg.1 DVAL.1
FDReg.0 DVAL.0