Datasheet

73S1215F Data Sheet DS_1215F_003
LOW
XTAL
OSC
VCO
Phase
Freq
DET
CPU CLOCK
DIVIDER
6 bits
MCLK
96MHz
LMCLK=32765Hz
1.5-48MHz
MPU CLOCK - CPCLK
SMART CARD LOGIC
BLOCK CLOCK
SCCLK
SCLK
CLOCK
Prescaler 6bits
SC/SCE
CLOCK
Prescaler 6bits
SEL
ETU CLOCK
DIVIDER
12 bits
div 2
CPUCKDiv
See SC Clock descriptions for more accurate diagram
ETUCLK
MCount(2:0)
KEYCLK
LCLK=32768Hz
X32IN
X32OUT
I2CCLK
1kHz
400kHz
USBCLK
48MHz
DIVIDE
by 120
DIVIDER
/2930
HIGH
XTAL
OSC
X12IN
X12OUT
M DIVIDER
/(2*N + 4)
HCLK
HOSCen
12.00MHz
32768Hz
12.00MHz
USBCKenb
div 2
ICLK
32KOSCenb
SCCKenb
SELSC
DIVIDE
by 96
CLK1M
1MHz
7.386MHz
7.386MHz
3.6923MHz
DIV
32
I2C_2x
800kHz
div 2
SCECLK
div 2
div 2
Mux
RTCCLK
Figure 3: Clock Generation and Control Circuits
24 Rev. 1.4